| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2016 | QB-trees: Towards an optimal topological representation and its applications to analog layout designs | Wu, I.-P.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 11 | 0 | |
| 1999 | Quasi-universal switch matrices for FPD design | Wu, G.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computers | 6 | 3 | |
| 2007 | Recent research and emerging challenges in physical design for manufacturability/reliability | Lin, C.-W.; Tsai, M.-C.; Lee, K.-Y.; Chen, T.-.; Wang, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 13 | 0 | |
| 2007 | Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. | Lin, Chung-Wei; Tsai, Ming-Chao; Lee, Kuang-Yao; Chen, Tai-Chen; Wang, Ting-Chi; YAO-WEN CHANG ; CHUNG-WEI LIN | Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007 | 13 | 0 | |
| 2016 | Recent research development and new challenges in analog layout synthesis | Lin, M.P.-H.; Chang, Y.-W.; Hung, C.-M.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 38 | 0 | |
| 2010 | Recent research development in flip-chip routing. | Lee, Hsu-Chieh; Chang, Yao-Wen; Lee, Po-Wei; YAO-WEN CHANG | 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010 | 15 | 0 | |
| 2005 | Reconfigurable platform for content science research | LIANG-GEE CHEN ; TEI-WEI KUO ; YAO-WEN CHANG ; SHAO-YI CHIEN ; CHIA-LIN YANG ; CHI-SHENG SHIH ; Ku, Mong-Kai | 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications | 0 | 0 |  |
| 2003 | Rectilinear block placement using B*-trees | Wu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 25 | 20 | |
| 2000 | Rectilinear block placement using B*-trees | Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 9 | | |
| 2000 | Rectilinear Block Placement Using B*-Trees. | Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000 | 0 | 0 | |
| 2016 | Redistribution layer routing for integrated fan-out wafer-level chip-scale packages | Lin, B.-Q.; Lin, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 11 | 0 | |
| 2017 | Redistribution layer routing for wafer-level integrated fan-out package-on-packages | Lin, T.-C.; Chi, C.-C.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 9 | 0 | |
| 2010 | Redundant-wires-aware ECO timing and mask cost optimization | Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 15 | 0 | |
| 2006 | Reliable crosstalk-driven interconnect optimization | Jiang, I.H.-R.; Pan, S.-R.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 2 | 1 | |
| 2006 | Reliable crosstalk-driven interconnect optimization | Jiang, I.H.-R.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG ; HUI-RU JIANG | ACM Transactions on Design Automation of Electronic Systems | 2 | 12 | |
| 2006 | Reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | ACM Trans. Design Autom. Electr. Syst. | 0 | 1 | |
| 2006 | Reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG | ACM Trans. Design Autom. Electr. Syst. | 0 | 1 | |
| 2006 | RLC coupling-aware simulation and on-chip bus encoding for delay reduction | Tu, S.-W.; Jou, J.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 37 | 23 | |
| 2005 | Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 6 | 0 | |
| 2004 | RLC effects on worst-case switching pattern for on-chip buses | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 10 | | |
