| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2010 | Unified analytical global placement for large-scale mixed-size circuit designs | Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 8 | 0 | |
| 2012 | Unified analytical global placement for large-scale mixed-size circuit designs | Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 17 | 16 | |
| 2020 | Unified Redistribution Layer Routing for 2.5D IC Packages | Chiang, C.-H.; Chuang, F.-Y.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | 0 | |
| 2004 | Universal switch blocks for three-dimensional FPGA design | Wu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG | IEE Proceedings: Circuits, Devices and Systems | 9 | 7 | |
| 1999 | Universal Switch Blocks for Three-Dimensional FPGA Design. | Wu, Guang-Ming; Shyu, Michael; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999 | 0 | 0 | |
| 1996 | Universal switch modules for fpga design | Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 101 | | |
| 1996 | Universal switch-module design for symmetric-array-based FPGAs | Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA | 20 | | |
| 1996 | Universal Switch-Module Design for Symmetric-Array-Based FPGAs. | Wong, D. F.; Wong, C. K.; YAO-WEN CHANG | Proceedings of the 1996 ACM 4th International Symposium on Field-Programmable Gate Arrays, FPGA 1996 | 20 | 0 | |
| 2016 | VCR: Simultaneous via-template and cut-template-aware routing for directed self-assembly technology | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 4 | 0 | |
| 1996 | A velocity-overshoot capacitance model for 0.1 μm MOS transistors | Kuo, J.B.; Chang, Y.W.; Lai, C.S.; YAO-WEN CHANG | Solid-State Electronics | 4 | 4 | |
| 2020 | Via-based redistribution layer routing for InFO packages with irregular pad structures | Wen, H.-T.; Cai, Y.-J.; Hsu, Y.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 6 | 0 | |
| 2021 | VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units | Chou Y; Hsu J.-W; Chen T.-C.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
| 2006 | Voltage Island aware floorplanning for power and timing optimization | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 74 | 0 | |
| 2006 | Voltage island aware floorplanning for power and timing optimization. | Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
| 2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 4 | | |
| 2011 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 3 | |
| 2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. | Chuang, Yi-Lin; Lee, Po-Wei; Chang, Yao-Wen; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 4 | 0 | |
| 2009 | Voltage-island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 10 | |
| 2009 | Voltage-Island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 10 | |
| 2018 | WB-trees: A meshed tree representation for FinFET analog layout designs | Lu, Y.-S.; Chang, Y.-H.; Chang, Y.-W. | Design Automation Conference | 5 | 0 | |
