公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2018 | A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control | Luo, Y.-S.; Lin, H.-H.; Liu, S.-I.; SHEN-IUAN LIU | 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings | 0 | 0 | |
2020 | A 13.56 MHz current-mode wireless power receiver with energy-investment capability | Kuo C.-J; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 1 | 2 | |
2011 | A 132.6-GHz phase-locked loop in 65 nm digital CMOS | Lin, B.-Y.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 10 | 7 | |
2003 | 1V 4.2mW Fully Integrated 2.5Gb/s CMOS Limiting Amplifier using Folded Active Inductors | Chia-Hsin Wu; Jieh-Wei Liao; Chih-Hun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | 2003 VLSI/CAD | | | |
2000 | A 2 V clock synchronizer using digital delay-locked loop | Hwang, Chorng-Sii; Chung, Wang-Chih; Wang, Chih-Yong; Tsao, Hen-Wai ; Liu, Shen-Iuan | Second IEEE Asia Pacific Conference on ASICs | 0 | 0 | |
2022 | A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator | Chang J.-R; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 2 | 2 | |
2017 | A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer with a Fast-Converging Correlation Loop | Tseng, Y.-H.; Yeh, C.-W.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 20 | 19 | |
2002 | 2.4 GHz offset-cancelling down-conversion mixer | Chih-Chun Tang; Kun-Hsien Li; Shen-Iuan Liu; SHEN-IUAN LIU | Electronics Letters | 5 | 4 | |
2021 | A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL with Loop Bandwidth Calibration | Lu Y.-R; SHEN-IUAN LIU ; Yang Y.-C; Kang H.-C; Chen C.-L; Chan K.-U; Lin Y.-H. | IEEE Transactions on Circuits and Systems II: Express Briefs | 5 | 5 | |
2020 | A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL | Chou M.-H; Liu S.-I.; SHEN-IUAN LIU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 8 | 8 | |
2019 | A 2.4-GHz frequency-drift-compensated phase-locked loop with 2.43 ppm/°C temperature coefficient | Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 4 | 3 | |
2006 | A 2.4GHz CMOS quadrature VCO for 2.4GHz WLAN/bluetooth applications | Chang, J.-Y.; Wu, C.-H.; Liu, S.-I.; SHEN-IUAN LIU | 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 | 7 | 0 | |
2007 | A 2.5 GHz all-digital delay-locked loop in 0.13 mu m CMOS technology | Yang, Rong-Jyi; Liu, Shen-Iuan; SHEN-IUAN LIU | Ieee Journal of Solid-State Circuits | 69 | 53 | |
2022 | A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR with One-Tap DFE | Chen W.-M; Yao Y.-S; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 1 | 1 | |
2010 | A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology | Kao, S.-Y.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 18 | 15 | |
2009 | A 20-MHz to 3-GHz wide-range multiphase delay-locked loop | Chuang, C.-N.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 23 | 20 | |
2011 | 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011: Foreword | Liu, S.-I.; SHEN-IUAN LIU | 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011 | 0 | | |
2008 | 20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13μm CMOS | Hong-Lin Chu; Chaung-Lin Hsieh; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits Conference (A-SSCC) | 4 | 0 | |
2010 | 258.16-259.95GHz injection-locked frequency divider | Lee, I.-T.; Wang, C.-H.; Lin, B.-Y.; Liu, S.-I.; SHEN-IUAN LIU | Electronics Letters | 11 | 9 | |
2015 | A 2×25 Gb/s clock and data recovery with background amplitude-locked loop | Kao, C.-K.; Fu, K.-L.; Liu, S.-I.; SHEN-IUAN LIU | Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 | 2 | 0 | |