公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2005 | A 0.1-25.5-GHz differential cascaded-distributed amplifier in 0.18-μm CMOS Technology | Chihun Lee; Lan-Chou Cho; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits | 12 | 0 | |
2008 | A 0.18-μm CMOS 1.25-Gbps automatic-gain-control amplifier | I-Hsin Wang; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 33 | 22 | |
2006 | A 0.18μm CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems | Yen-Horng Chen; Chih-Wei Wang; Ching-Feng Lee; Jen-Lung Liu; Tzu-Yi Yang; Chih-Fan Liao; Che-Fu Liang; Gin-Kou Ma; Shen-Iuan Liu; SHEN-IUAN LIU | 2006 RFIC Symposium | | | |
2007 | A 0.5-5-GHz wide-range multiphase DLL with a calibrated charge pump | Chi-Nan Chuang; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 48 | 44 | |
2006 | A 0.7-2-GHz self-calibrated multiphase delay-locked loop | Hsiang-Hui Chang; Jung-Yu Chang; Chun-Yi Kuo; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 47 | 37 | |
2002 | A 0.8 V switched-opamp bandpass ΔΣ modulator using a two-path architecture | Hsiang-Hui Chang; Shang-Ping Chen; Kuang-Wei Cheng; SHEN-IUAN LIU | 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings | 2 | 0 | |
2006 | A 1 v phase locked loop with leakage compensation in 0.13 μm CMOS technology | Chi-Nan Chuang; Shen-Iuan Liu; SHEN-IUAN LIU | IEICE Transactions on Electronics | 10 | 6 | |
2004 | A 1-V 10.7-MHz fourth-order bandpass Delta Sigma modulators using two switched opamps | Chien-Hung Kuo; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 13 | 10 | |
2010 | A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression | Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU | International Symposium on VLSI Design, Automation & Test | 10 | 0 | |
2006 | A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology | Chihun Lee; Lan-Cho Chou; Shen-Iuan Liu; Chun-Lin Ko; Ying-Zong Juang; Chin-Fong Chiu; SHEN-IUAN LIU | 2006 Symposium on VLSI Circuits | 4 | 0 | |
2007 | A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology | Lan-Chou Cho; Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 4 | | |
2004 | A 1.2V, 18mW, 10Gb/s SiGe transimpedance amplifier | Lee, Chihun; Wu, Chia-Hsin; Liu, Shen-Iuan | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | 0 | 0 | |
2009 | A 1.5GHz all-digital spread spectrum clock generator | Sheng-You Lin; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 56 | 44 | |
2009 | A 1.5GHz phase-locked loop with leakage current suppression in 65nm CMOS | Jung-Yu Chang; Shen-Iuan Liu; SHEN-IUAN LIU | IET Circuits, Devices & Systems | 6 | 3 | |
2004 | A 1.5V 12-bit 16MS/s pipelined CMOS ADC with 68dB dynamic range | Ming-Huang Liu; Wei-Yang Ou; Tsung-Yi Su; Kuo-Chan Huang; Shen-Iuan Liu; SHEN-IUAN LIU | Journal of Analog Integrated Circuits and Signal Processings | 7 | 4 | |
2010 | A 1.62/2.7-Gb/s adaptive transmitter with two-tap preemphasis using a propagation-time detector | Shih-Yuan Kao; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 10 | 10 | |
2004 | A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector | Yang, Rong-Jyi; Liu, Shen-Iuan | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | 0 | 0 | |
2007 | A 10-bit 100MS/s pipelined ADC in 0.18μm CMOS technology | Hwei-Yu Lee; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE International SOC Conference | 2 | 0 | |
2013 | A 10-Gb/s adaptive parallel receiver with joint XTC and DFE using power detection | Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 12 | 10 | |
2010 | A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing | Huang, Mu-Chen; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 15 | 13 | |