公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2022 | Efficient Bad Block Management with Cluster Similarity | Yen J.-N; Hsieh Y.-C; Chen C.-Y; Chen T.-Y; CHIA-LIN YANG ; Cheng H.-Y; Luo Y. | Proceedings - International Symposium on High-Performance Computer Architecture | 2 | 0 | |
2007 | Efficient obstacle-avoiding rectilinear steiner tree construction. | Lin, Chung-Wei; Chen, Szu-Yu; Li, Chi-Feng; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG ; CHUNG-WEI LIN | Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007 | 36 | 0 | |
2017 | Enabling fast preemption via dual-kernel support on GPUs | Shieh, L.-W.; Chen, K.-C.; Fu, H.-C.; Wang, P.-H.; CHIA-LIN YANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
2008 | Energy-aware flash memory management in virtual memory system | CHIA-LIN YANG ; Li, Han-Lin; Yang, Chia-Lin; Tseng, Hung-Wei; CHIA-LIN YANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | | | |
2005 | Energy-efficient cache architecture for multimedia applications | CHIA-LIN YANG ; Yang, Chia-Lin; Lee, Chien-hao; Tseng, Hung-Wei; CHIA-LIN YANG | Emerging Information Technology Conference 2005 | | | |
2004 | Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism | Wu, Chin-Hsien; TEI-WEI KUO ; CHIA-LIN YANG | Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004 | 8 | | |
2004 | Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism | Wu, Chin-Hsien; Kuo, Tei-Wei ; Yang, Chia-Lin | Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis | | | |
2007 | Energy-Efficient Real-Time Task Scheduling with Task Rejection | Chen, Jian-Jia; Kuo, Tei-Wei ; Yang, Chia-Lin ; King, Ku-Jei | Design, Automation & Test in Europe Conference & Exhibition | 12 | 0 | |
2006 | An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage | Tseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin | 2006 International Symposium on Low Power Electronics and Design | | | |
2006 | An energy-efficient virtual memory system with flash memory as the secondary storage. | Tseng, Hung-Wei; Li, Han-Lin; CHIA-LIN YANG | Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 | | | |
1998 | Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications | CHIA-LIN YANG ; Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG | Annual International Symposium on Microarchitecture | | | |
1998 | Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. | Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG | Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998 | | | |
2000 | Exploiting parallelism in geometry processing with general purpose processors and floating-point SIMD instructions | CHIA-LIN YANG ; Yang, C.-L.; Sano, B.; Lebeck, A.R.; CHIA-LIN YANG | IEEE Transactions on Computers | | | |
2017 | Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives | Chang, C.-W.; Chen, G.-Y.; Chen, Y.-J.; Yeh, C.-W.; Eng, P.Y.; Cheung, A.; Yang, C.-L.; CHIA-LIN YANG | IEEE Transactions on Computers | | | |
2013 | Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. | Lin, Ping-Sheng; Chen, Yi-Jung; Yang, Chia-Lin; YI-CHANG LU ; CHIA-LIN YANG | International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013 | 2 | 0 | |
2019 | Fair Down to the Device: A GC-Aware Fair Scheduler for SSD. | Ji, Cheng; Wang, Lun; Li, Qiao; Gao, Congming; Shi, Liang; Yang, Chia-Lin; Xue, Chun Jason; CHIA-LIN YANG | 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2019, Hangzhou, China, August 18-21, 2019 | | | |
2015 | Fine-grained write scheduling for PCM performance improvement under write power budget. | Lai, Chun-Hao; Yu, Shun-Chih; Yang, Chia-Lin; CHIA-LIN YANG | IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 2015 | 6 | 0 | |
2020 | FlashEmbedding: Storing embedding tables in SSD for large-scale recommender systems | Wan H; Sun X; Cui Y; CHIA-LIN YANG ; TEI-WEI KUO ; Xue C.J. | APSys 2021 - Proceedings of the 12th ACM SIGOPS Asia-Pacific Workshop on Systems | 9 | 0 | |
2022 | A Forward Speculative Interference Attack | CHIA-LIN YANG ; Vetter, Ron | Computer | 0 | 0 | |
2014 | Full system simulation framework for integrated CPU/GPU architecture | Wang, P.-H.; Liu, G.-H.; Yeh, J.-C.; Chen, T.-M.; Huang, H.-Y.; Yang, C.-L.; Liu, S.-L.; CHIA-LIN YANG | Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test | 6 | 0 | |