公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2013 | Fault Scrambling Techniques for Yield Enhancement of Embedded Memories | S.-K. Lu; H.-C. Jheng; M. Hashizume; J.-L. Huang; P. Ning; JIUN-LANG HUANG | Asian Test Symposium | 5 | 0 | |
2013 | Foreword | Wang, S.-J.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 0 | 0 | |
2018 | Foreword: 26th IEEE Asian test symposium (ATS 2017) | Huang, J.-L.; Li, J.-F.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 0 | 0 | |
2011 | FPAA implementation and validation of an SC integrator leakage measurement technique | Du, N.-T.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 0 | 0 | |
2019 | An FPGA-Based Data Receiver for Digital IC Testing. | Huang, Wei-Chen; Hou, Guan-Hao; Huang, Jiun-Lang; Kuo, Terry; JIUN-LANG HUANG | IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019 | 3 | 0 | |
2014 | FPGA-Based Subset Sum Delay Lines | C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2020 | Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model | Chen, C.-Y.; Cheng, C.-H.; JIUN-LANG HUANG ; Chakrabarty, K. | Proceedings of the European Test Workshop | 3 | 0 | |
2011 | Guest Editors' Introduction: A Promising Alternative to Conventional Silicon | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | Ieee Design & Test of Computers | 0 | 1 | |
2011 | Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs | Huang, X.-L.; Kang, P.-Y.; Yu, Y.-C.; Huang, J.-L.; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | 3 | 2 | |
2011 | Image-quality-driven metrics for testing and calibrating ADC array in CMOS imagers: A first step | Chang, H.-M.; Cheng, K.-T.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 0 | 0 | |
2013 | Implementation of programmable delay lines on off-the-shelf FPGAs | Y.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | IEEE AUTOTESTCON | 8 | 0 | |
2013 | Improve speed path identification with suspect path expressions | J.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 0 | 0 | |
2010 | Improved weight assignment for logic switching activity during at-speed test pattern generation | Wu, M.-F.; Pan, H.-C.; Wang, T.-H.; Huang, J.-L.; Tsai, K.-H.; Cheng, W.-T.; JIUN-LANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 33 | 0 | |
2004 | An Infrastructure IP for On-Chip Clock Jitter Measurement. | Huang, Jui-Jer; Huang, Jiun-Lang; JIUN-LANG HUANG | 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings | 0 | 0 | |
2020 | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration | Jiang I.H.-R; Chang Y.-W; Huang J.-L; CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 5 | 0 | |
2016 | An IR-drop aware test pattern generator for scan-based at-speed testing | P.-F. Hou; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
2016 | An IR-drop guided test pattern generation technique | L.-C. Tsai; J.-Z. Li; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation and Test | 4 | 0 | |
2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | CHIEN-MO LI ; JIUN-LANG HUANG ; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | | 0 | |
2009 | Logic and Circuit Simulation | Huang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG | Electronic Design Automation | 2 | 0 | |
2006 | Logic and fault simulation | Huang, J.-L. ; Li, J.C.-M. ; Walker, D.M. | VLSI Test Principles and Architectures | 0 | 0 | |