公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2011 | Image-quality-driven metrics for testing and calibrating ADC array in CMOS imagers: A first step | Chang, H.-M.; Cheng, K.-T.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 0 | 0 | |
2013 | Implementation of programmable delay lines on off-the-shelf FPGAs | Y.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | IEEE AUTOTESTCON | 8 | 0 | |
2013 | Improve speed path identification with suspect path expressions | J.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 0 | 0 | |
2010 | Improved weight assignment for logic switching activity during at-speed test pattern generation | Wu, M.-F.; Pan, H.-C.; Wang, T.-H.; Huang, J.-L.; Tsai, K.-H.; Cheng, W.-T.; JIUN-LANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 33 | 0 | |
2004 | An Infrastructure IP for On-Chip Clock Jitter Measurement. | Huang, Jui-Jer; Huang, Jiun-Lang; JIUN-LANG HUANG | 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings | 0 | 0 | |
2020 | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration | Jiang I.H.-R; Chang Y.-W; Huang J.-L; CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 5 | 0 | |
2016 | An IR-drop aware test pattern generator for scan-based at-speed testing | P.-F. Hou; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
2016 | An IR-drop guided test pattern generation technique | L.-C. Tsai; J.-Z. Li; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation and Test | 4 | 0 | |
2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | 0 | 0 | |
2009 | Logic and Circuit Simulation | Huang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG | Electronic Design Automation | 2 | 0 | |
2006 | Logic and fault simulation | Huang, J.-L. ; Li, J.C.-M. ; Walker, D.M. | VLSI Test Principles and Architectures | 0 | 0 | |
2009 | LPTest: A Flexible Low-Power Test Pattern Generator | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 7 | 5 | |
2013 | METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME | Hung-I Chen; Chang-Yu Chen; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG | | | | |
2016 | A multi-channel FPGA-based time-to-digital converter | L.-Y. Hsu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signal Testing Workshop | 1 | 0 | |
2019 | A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction | Li, B.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - International SoC Design Conference 2018, ISOCC 2018 | 0 | 0 | |
2013 | On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression | K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG | International Conference on VLSI Design | 5 | 0 | |
2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
2011 | On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imager | Huang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 1 | 0 | |
2002 | On-Chip Analog Response Extraction with 1-Bit Sigma-Delta Modulators | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; JIUN-LANG HUANG | Asian Test Symposium | 11 | 0 | |
2006 | On-chip random jitter testing using low tap-count coarse delay lines | JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | 2 | 1 | |