公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2000 | Test point selection for analog fault diagnosis of unpowered circuit boards | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 18 | 16 | |
2022 | Test Response Compaction for Software-Based Self-Test | Liang, Jia Ruei; Hsieh, Ya Ni; JIUN-LANG HUANG | Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 | 0 | 0 | |
2019 | Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime | Chen, K.-H.; Chen, C.-Y.; JIUN-LANG HUANG | Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 | 3 | 0 | |
2012 | Testing and calibration of SAR ADCs by MCT-based bit weight extraction | Huang, X.-L.; Chen, H.-I.; Huang, J.-L.; Chen, C.-Y.; Kuo-Tsai, T.; Huang, M.-F.; Chou, Y.-F.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | 7 | 0 | |
2000 | Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000 | 0 | 0 | |
2008 | Testing LCD Source Driver IC with Built-On-Scribe-Line Test Circuitry | J.-J. Huang; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
2002 | Testing Second-Order Delta-Sigma Modulators using Pseudo-Random Patterns | C. K. Ong; J. L. Huang; K. T. Cheng; JIUN-LANG HUANG | Microelectronics Journal | 6 | 3 | |
2012 | Time-resolved and temperature-varied photoluminescence studies of InGaN/GaN multiple quantum well structures | Liu, L.; Wang, W.; Huang, J.-L.; Hu, X.; Chen, P.; Huang, J.-J.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | 4 | 0 | |
2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 | |
2012 | Welcome message | Wu, C.-W.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | 0 | 0 | |
2022 | Welcome Message ITC-Asia 2022 | Chang, Soon Jyh; JIUN-LANG HUANG | Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 | 0 | 0 | |
2008 | 可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(1/3) | 黃俊郎 | | | | |
2008 | 可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(2/3) | 黃俊郎 | | | | |
2008 | 多媒體系統無線傳輸介面之研發-子計畫五:以內建自我測試為基礎的ADC/DAC校正與修復技術之研發(1/3) | 黃俊郎 | | | | |
2003 | 子計劃六:可重組化運算之測試設計(I) | 黃俊郎 | | | | |
2004 | 子計畫三:高速資料傳輸系統的可測試性設計技術(1/3) | 黃俊郎 | | | | |
2005 | 子計畫三:高速資料傳輸系統的可測試性設計技術(2/3) | 黃俊郎 | | | | |
2004 | 子計畫四:類比前端電路的內建自我測試技術 | 黃俊郎 | | | | |
2014 | 數位類比轉換器的元素的權重的估算方法、裝置及應用其之逐次逼近暫存 器類比數位轉換器 | 陳弘易; 陳昶聿; 黃炫倫; 黃俊郎; JIUN-LANG HUANG | | | | |
2013 | 測試圖案最佳化的方法 | JIUN-LANG HUANG ; 吳孟帆; 黃俊郎; 溫曉青; 宮瀨紘平 | | | | |