公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2005 | Effective and Economic Phase Noise Testing for Single Chip TV Tuners | CHIEN-MO LI ; P.C. Lin; J. C.-M. Li; Chih-Ming Chiang; Chuo-Jan Pan; CHIEN-MO LI | VLSI/CAD Symposium | | | |
2008 | Effective and Economic Phase Noise Testing for Single-Chip TV Tuners | CHIEN-MO LI ; J. C.-M. Li; P.-C. Lin; P.-C. Chiang; C.-M. Pan; C.W. Tseng; CHIEN-MO LI | IEEE Transactions on Instrumentation and Measurement | | 0 | |
2018 | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction | Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI | Design Automation Conference | 5 | 0 | |
2009 | Electronic Design Automation | CHIEN-MO LI ; J. C.-M. Li; M. Hsiao; CHIEN-MO LI | | | | |
2004 | ELF-Murphy Data on Defects and Test Sets | CHIEN-MO LI ; E. J. McCluskey; A. Alyamani; J. C. M. Li; C. W. Tseng; E. Volkerink; F. F. Feriani; E. Li; S. Mitra; CHIEN-MO LI | IEEE VLSI Test Symposium | | | |
2002 | Experimental Results for Slow Speed Testing | CHIEN-MO LI ; C.W.Tseng; J.C.M. Li; E. J. McCluskey; CHIEN-MO LI | IEEE VLSI Test Symposium | | | |
2009 | Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs | CHIEN-MO LI ; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI | Asia and South Pacific Design Automation Conference, ASP-DAC | | | |
2021 | Fault Modeling and Testing of Spiking Neural Network Chips | Hsieh, Yi Zhan; Tseng, Hsiao Yin; Chiu, I. Wei; CHIEN-MO LI | Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 | 2 | 0 | |
2009 | Fault Simulation and Test Generation | CHIEN-MO LI ; Li, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI | Electronic Design Automation | | | |
2015 | Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits | Chiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 9 | 0 | |
2013 | Fault Simulation and Test Pattern Selection for Small Delay Defect Using GPU | CHIEN-MO LI ; SC Hsu; KY Liao; CHIEN-MO LI | VLSI/CAD | | | |
2014 | Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects | E. H. Ma; W. E. Wei; H. Y. Li; J. C. M. Li; I. C. Cheng; Y. H. Yeh; I-CHUN CHENG ; CHIEN-MO LI | IEEE Journal of Display Technology | 3 | 3 | |
2012 | Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects | CHIEN-MO LI ; EH Ma; WE Wei; CHIEN-MO LI | VLSI/CAD | | | |
2014 | GALAXY: A Multi-Circuit Simulator based on Inverse Jacobian Matrix Reuse | CHIEN-MO LI ; H.Y. Lee; C.Y. Han; CHIEN-MO LI | IEEE/ACM Design Automation Conference | | | |
2012 | GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG | CHIEN-MO LI ; KY Liao; SC Hsu; CHIEN-MO LI | IEEE Int’l Test Conf. | | | |
2012 | GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG, | CHIEN-MO LI ; K. Y. Liao; S. C. Hsu; CHIEN-MO LI | Design Automation Conference | | | |
2014 | GPU-Based Timing-Aware Test Generation for Small Delay Defects | CHIEN-MO LI ; K.Y. Liao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI | IEEE European Test Symposium | | | |
2014 | GPU-based timing-aware test generation for small delay defects. | CHIEN-MO LI ; Liao, Kuan-Yu; Chen, Po-Juei; Lin, Ang-Feng; Li, James Chien-Mo; Hsiao, Michael S.; Wang, Laung-Terng; CHIEN-MO LI | 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014 | | | |
2020 | High Efficiency and Low Overkill Testing for Probabilistic Circuits | CHIEN-MO LI ; Lee M.-T; Wu C.-H; Liu S.-T; Hsieh C.-Y; CHIEN-MO LI | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | | | |
2023 | High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns | Liang, Zhe Jia; Wu, Yu Tsung; Yang, Yun Feng; CHIEN-MO LI ; Chang, Norman; Kumar, Akhilesh; Li, Ying Shiun | Proceedings - International Test Conference | | | |