公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2009 | Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs | B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI | Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
2021 | Fault Modeling and Testing of Spiking Neural Network Chips | Hsieh, Yi Zhan; Tseng, Hsiao Yin; Chiu, I. Wei; CHIEN-MO LI | Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 | 2 | 0 | |
2009 | Fault Simulation and Test Generation | Li, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI | Electronic Design Automation | 2 | 0 | |
2015 | Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits | Chiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 9 | 0 | |
2013 | Fault Simulation and Test Pattern Selection for Small Delay Defect Using GPU | SC Hsu; KY Liao; JCM Li; CHIEN-MO LI | VLSI/CAD | | | |
2012 | Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects | EH Ma; WE Wei; JCM Li; CHIEN-MO LI | VLSI/CAD | 3 | 3 | |
2014 | Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects | E. H. Ma; W. E. Wei; H. Y. Li; J. C. M. Li; I. C. Cheng; Y. H. Yeh; I-CHUN CHENG ; CHIEN-MO LI | IEEE Journal of Display Technology | 3 | 3 | |
2014 | GALAXY: A Multi-Circuit Simulator based on Inverse Jacobian Matrix Reuse | H.Y. Lee; C.Y. Han; J. C.-M. Li; CHIEN-MO LI | IEEE/ACM Design Automation Conference | | | |
2012 | GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG | KY Liao; SC Hsu; JCM Li; CHIEN-MO LI | IEEE Int’l Test Conf. | | | |
2012 | GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG, | K. Y. Liao; S. C. Hsu; J. C. M. Li; CHIEN-MO LI | Design Automation Conference | 12 | 0 | |
2014 | GPU-Based Timing-Aware Test Generation for Small Delay Defects | K.Y. Liao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI | IEEE European Test Symposium | 5 | 0 | |
2014 | GPU-based timing-aware test generation for small delay defects. | Liao, Kuan-Yu; Chen, Po-Juei; Lin, Ang-Feng; Li, James Chien-Mo; Hsiao, Michael S.; Wang, Laung-Terng; CHIEN-MO LI | 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014 | 5 | 0 | |
2020 | High Efficiency and Low Overkill Testing for Probabilistic Circuits | Lee M.-T; Wu C.-H; Liu S.-T; Hsieh C.-Y; Li J.C.-M.; CHIEN-MO LI | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | 1 | 0 | |
2023 | High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns | Liang, Zhe Jia; Wu, Yu Tsung; Yang, Yun Feng; CHIEN-MO LI ; Chang, Norman; Kumar, Akhilesh; Li, Ying Shiun | Proceedings - International Test Conference | | | |
1998 | IDDQ data analysis using current signature | Li, J.C.M.; McCluskey, E.J.; CHIEN-MO LI | Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998 | 12 | 0 | |
2008 | IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores | Geng-Ming Chiu; C.-Y. Chiu; R-Y. Wen; James Chien-Mo Li; CHIEN-MO LI | International Test Conference | 4 | 0 | |
2021 | Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization | Wu M.-T; Kuo C.-S; Li J.C.-M; Nigh C; Bhargava G.; CHIEN-MO LI | Proceedings - International Test Conference | 0 | 0 | |
2018 | IR drop prediction of ECO-revised circuits using machine learning | Lin, S.-Y.; Fang, Y.-C.; Li, Y.-C.; Liu, Y.-C.; Yang, T.-S.; Lin, S.-C.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI | Proceedings of the IEEE VLSI Test Symposium | 16 | 0 | |
2005 | Jump Scan: A DFT Technique for Low Power Testing, | M.H. Chiu; J. C. M Li; CHIEN-MO LI | IEEE VLSI Test Symposium | 39 | 0 | |
2006 | Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique | Y. L Kao; W. S. Chuang; J. C. M Li; CHIEN-MO LI | IEEE International Test Conference | 33 | 0 | |