公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2005 | Jump Scan: A DFT Technique for Low Power Testing, | M.H. Chiu; J. C. M Li; CHIEN-MO LI | IEEE VLSI Test Symposium | 39 | 0 | |
2006 | Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique | Y. L Kao; W. S. Chuang; J. C. M Li; CHIEN-MO LI | IEEE International Test Conference | 33 | 0 | |
2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | 0 | 0 | |
2006 | Logic and fault simulation | Huang, J.-L. ; Li, J.C.-M. ; Walker, D.M. | VLSI Test Principles and Architectures | 0 | 0 | |
2022 | Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor | Liu, Shi Tang; Chen, Jia Xian; Wu, Yu Tsung; Hsieh, Chao Ho; CHIEN-MO LI ; Chang, Norman; Li, Ying Shiun; Chuang, Wen Tze | Proceedings - International Symposium on Quality Electronic Design, ISQED | 0 | 0 | |
2018 | Machine-learning-based dynamic IR drop prediction for ECO | Fang, Y.-C.; Lin, H.-Y.; Su, M.-Y.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 38 | 0 | |
2010 | Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium | J. Y. Wen; J. C. M. Li; CHIEN-MO LI | | | | |
2021 | Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning | Kuo Y.-T; Lin W.-C; Chen C; Hsieh C.-H; Li J.C.-M; Jia-Wei Fang E; Hsueh S.S.-Y.; CHIEN-MO LI | Proceedings - International Test Conference | 3 | 0 | |
2022 | ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption | Lin, Wei Chen; Chen, Chun; Hsieh, Chao Ho; CHIEN-MO LI ; Fang, Eric Jia Wei; Hsueh, Sung S.Y. | Proceedings - International Test Conference | 1 | 0 | |
2012 | Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs | B. C. Bai; J. C. M. Li; CHIEN-MO LI | ITC | | | |
2016 | A multicircuit simulator based on inverse jacobian matrix reuse | Lee, H.-I.; Han, C.-Y.; Li, J.C.-M.; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
2015 | The Multimedia Piers-Harris Children's Self-Concept Scale 2: Its Psychometric Properties, Equivalence with the Paper-and-Pencil Version, and Respondent Preferences | Flahive, Mon-hsin Wang; Chuang, Ying-Chih; Li, Chien-Mo; CHIEN-MO LI | Plos One | 10 | 8 | |
2018 | A new method for parameter estimation of high-order polynomial-phase signals. | Cao, Runqing; Li, James Chien-Mo; Zuo, Lei; Wang, Zeyu; Lu, Yunlong; CHIEN-MO LI | Signal Processing | 18 | 17 | |
2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
2018 | Parallel order ATPG for test compaction | Chen, Y.-W.; Ho, Y.-H.; Chang, C.-M.; Yang, K.-C.; Li, M.-T.; Li, J.C.-M.; CHIEN-MO LI | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 | 5 | 0 | |
2008 | Phase Noise Testing of Single Chip TV Tuners, | P.-C. Lin; C.-H. Hsu; J. C.-M. Li; C.-M. Chiang; C.-J. Pan,; CHIEN-MO LI | IEEE VLSI-DAT | 0 | 0 | |
2017 | Physical-aware diagnosis of multiple interconnect defects | Chen, P.-H.; Lee, C.-L.; Chen, J.-Y.; Chen, P.-W.; CHIEN-MO LI | ITC-Asia 2017 - International Test Conference in Asia | 2 | 0 | |
2014 | Physical-aware Systematic Multiple Defect Diagnosis | P. J. Chen; C. C. Che; J. C. M. Li; S. F. Kuo; P. Y. Hsueh; C. Y. Kuo; J. N. Lee; CHIEN-MO LI | IET Proceedings Computers and Digital Techniques | 12 | 10 | |
2011 | Placement optimization of flexible TFT digital circuits | Liu, W.-H.; Ma, E.-H.; Wei, W.-E.; Li, J.C.-M.; CHIEN-MO LI | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 1 | 0 | |
2011 | Placement optimization of flexible TFT digital circuits | Liu, C.; Ma, E.-H.; Wei, W.-E.; Li, J.; Cheng, I.-C.; Yeh, Y.-H.; I-CHUN CHENG ; CHIEN-MO LI | IEEE Design and Test of Computers | 4 | 4 | |