公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2011 | Reliability and Validity Evidence of the Chinese Piers-Harris Children's Self-Concept Scale Scores Among Taiwanese Children | Flahive, Mon-hsin Wang; Chuang, Ying-Chih; Li, Chien-Mo; CHIEN-MO LI | Journal of Psychoeducational Assessment | 9 | 7 | |
2010 | Reliability screening of a-Si TFT circuits: Very-low voltage and I <inf>DDQ</inf> Testing | Shen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG ; CHIEN-MO LI | IEEE/OSA Journal of Display Technology | 2 | 1 | |
2007 | Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique | B.-H. Chen; Wei-Chuang Kao; Bin-Chuan Bai; Shyue-Tsong Shen; James C.-M. Li; CHIEN-MO LI | IEEE Asian Test Symposium | 0 | 0 | |
2017 | Robust test pattern generation for hold-time faults in nanometer technologies | Ho, Y.-H.; Chen, Y.-W.; Chang, C.-M.; Yang, K.-C.; Li, J.C.-M.; CHIEN-MO LI | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 | 1 | 0 | |
2010 | Row-LFSR-Column (RLC) Test Response Masking Technique | WC Wang; JCM Li; CHIEN-MO LI | VLSI/CAD | | | |
2011 | Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips | W.C. Wang; J.C.M Li; CHIEN-MO LI | IET Computers & Digital Techniques | 2 | 2 | |
2005 | Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing | Lee, C-Y; Li, C-M; CHIEN-MO LI | Asia Solid-State Circuit Conference (ASSCC) | 1 | 0 | |
2008 | Simultaneous capture and shift power reduction test pattern generator for scan testing | H.T. Lin; J. C.M. Li; CHIEN-MO LI | IET Computers & Digital Techniques | 13 | 12 | |
2014 | Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics | Y. L. Chen; W. R. Wu; C. N. J. Liu; J. C. M. Li; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 22 | 16 | |
2023 | Small Sampling Overhead Error Mitigation for Quantum Circuits | Hsieh, Cheng Yun; Tsai, Hsin Ying; Lu, Yuan Hsiang; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
2010 | Static timing analysis for flexible TFT circuits | Chao-Hsuan Hsu; Liu, C.; En-Hua Ma; Li, J.C.-M.; CHIEN-MO LI | Design Automation Conference (DAC) | 5 | 0 | |
2012 | Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis | W.L. Tsai; J. C.M. Li; CHIEN-MO LI | IEEE Transactions on Computers | 9 | 9 | |
2020 | Student engagement in the co-designing and co-teaching a cornerstone eecs design and implementation course at national Taiwan university | Lee, Jennifer Wen-Shya et al.; Lin, Kun-You ; Chen, Ho-Lin ; Chen, J.-P.; SHIH-YUAN CHEN ; CHIEN-MO LI ; Xu, R.-F.; TZI-DAR CHIUEH ; HSIAO-WEN CHUNG ; Chen, N.; SHI-CHUNG CHANG | International Conference on Higher Education Advances | 0 | 0 | |
2008 | Survey of Scan Chain Diagnosis | Y. Huang; R Guo; W.T. Cheng; J. C.-M. Li; CHIEN-MO LI | IEEE Design & Test of Computers | 68 | 55 | |
2020 | Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips | Liu C.-Y; Wu M.-T; Li J.C.-M; Bhargava G; Nigh C.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 1 | 0 | |
2012 | Systematic Open Via Diagnosis Based on Physical Features | P. J. Chen; C. C. Che; J. C. M. Li; K. Y. Tsai; S. F. Kuo; P. Y. Hsueh; Y. Y. Chen; J. N. Lee; CHIEN-MO LI | IEEE Silicon Debug and Diagnosis Workshop | | | |
2015 | TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for Cell-internal Defects | A.F. Lin; Kuan-Yu Liao; Kuan-Ying Chiang; James Chien-Mo Li; CHIEN-MO LI | IEEE VLSI/DAT | 5 | 0 | |
2013 | Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering | Y. C. Huang; M. H. Tsai; W. S. Ding; J. C. M. Li; M. T. Chang; M. H. Tsai; C. M. Tseng; H. C. Li; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 7 | 6 | |
2013 | Test generation of path delay faults induced by defects in power TSV | Shih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; TZONG-LIN WU ; YI-CHANG LU ; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 2 | 0 | |
2013 | Test Generation of Path Delay Faults Induced by Defects in Power TSV | Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI | IEEE Asian Test Symposium | 2 | 0 | |