公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2019 | Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. | Chang, Yi-Fan Evan; Huang, Ruei-Yang; Jiang, Jie-Hong R.; JIE-HONG JIANG | 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019 | 8 | 0 | |
2018 | Efficient Computation of ECO Patch Functions | A. Q. Dao; N.-Z. Lee; L.-C. Chen; P.-H. Lin; J.-H. R. Jiang; A. Mishchenko; R. K. Brayton; JIE-HONG JIANG ; 江介宏 | Design Automation Conference (DAC) | 14 | 0 | |
2015 | Efficient Extraction of QBF (Counter)models from Long-Distance Resolution Proofs | Valeriy Balabanov; Jie-Hong R. Jiang; Mikolas Janota; Magdalena Widl; JIE-HONG JIANG | AAAI Conference on Artificial Intelligence (AAAI-15) | 22 | | |
2018 | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction | Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI | Design Automation Conference | 5 | 0 | |
2005 | Efficient Solution of Language Equations Using Partitioned Representations | Alan Mishchenko; Robert K. Brayton; Jie-Hong R. Jiang; Tiziano Villa; Nina Yevtushenko; JIE-HONG JIANG | Design Automation and Test in Europe (DATE'05) | 7 | 0 | |
2013 | Encoding Multi-Valued Functions for Symmetry | Ko-Lung Yuan; Chien-Yen Kuo; Jie-Hong R. Jiang; Meng-Yen Li; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | | | |
2013 | Encoding multi-valued functions for symmetry. | Yuan, Ko-Lung; Kuo, Chien-Yen; Jiang, Jie-Hong R.; Li, Meng-Yen; JIE-HONG JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013 | 1 | 0 | |
2022 | Encoding Probabilistic Graphical Models into Stochastic Boolean Satisfiability | Hsieh, Cheng Han; JIE-HONG JIANG | IJCAI International Joint Conference on Artificial Intelligence | 1 | | |
2020 | Engineering Change Order for Combinational and Sequential Design Rectification | Jiang, J.-H.R.; Kravets, V.N.; Lee, N.-Z.; JIE-HONG JIANG | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 | 8 | 0 | |
2011 | Extracting Functions from Boolean Relations Using SAT and Interpolation | Jie-Hong Rol; Jiang, Hsuan-Po Lin; Wei-Lun Hung; JIE-HONG JIANG | | | | |
2011 | Extracting functions from boolean relations using SAT and interpolation | Jiang, J.-H.R.; Lin, H.-P.; Hung, W.-L.; JIE-HONG JIANG | Advanced Techniques in Logic Synthesis, Optimizations and Applications | 0 | 0 | |
2016 | Flexibility and Optimization of QBF Skolem-Herbrand Certificates | Valeriy Balabanov; Shuo-Ren Lin; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
2004 | Functional Dependency for Verification Reduction | Jie-Hong R. Jiang; Robert K. Brayton; JIE-HONG JIANG | Int'l Conf. on Computer Aided Verification (CAV'04) | 18 | | |
2004 | Functional dependency for verification reduction | Jiang, J.-H.R.; Brayton, R.K.; JIE-HONG JIANG | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | 18 | | |
2004 | Functional Dependency for Verification Reduction. | Jiang, Jie-Hong Roland; Brayton, Robert K.; JIE-HONG JIANG | Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings | 18 | 0 | |
2012 | Functional Timing Analysis Made Fast and General | Yi-Ting Chung; Jie-Hong R. Jiang; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC'12) | 4 | 7 | |
2013 | Functional Timing Analysis Made Fast and General | Yi-Ting Chung; Jie-Hong R. Jiang; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) | 9 | 7 | |
2017 | A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning | Hsiao-Lei Chien; Mei-Yen Chiu; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | IEEE Transaction on CAD of Integrated Circuits and Systems | 0 | 0 | |
2010 | Hardware Equivalence and Property Verification | Jie-Hong R. Jiang; Tiziano Villa; JIE-HONG JIANG | | | | |
2010 | Hardware Equivalence and Property Verification. | Jiang, Jie-Hong Roland; Villa, Tiziano; Crama, Yves; Hammer, Peter L.; JIE-HONG JIANG | Boolean Models and Methods in Mathematics, Computer Science, and Engineering | | | |