公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2018 | Recent research and challenges in multiple patterning layout decomposition | Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI | 0 | 0 | |
2011 | Recent research development in metal-only ECO | Tan, C.-Y.; Jiang, I.H.-R.; HUI-RU JIANG | Midwest Symposium on Circuits and Systems | 3 | 0 | |
2016 | Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits | Schlichtmann, U.; Hashimoto, M.; Jiang, I.H.-R.; Li, B.; HUI-RU JIANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | 0 | |
2012 | Reliability-driven power/ground routing for analog ICs | Lin, J.-W.; Ho, T.-Y.; Jiang, I.H.-R.; HUI-RU JIANG | ACM Transactions on Design Automation of Electronic Systems | 4 | 2 | |
2006 | Reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | ACM Trans. Design Autom. Electr. Syst. | 0 | 2 | |
2016 | Resource-aware functional ECO patch generation | Cheng, A.-C.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG | Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 | 11 | | |
2020 | Routing topology and time-division multiplexing co-optimization for multi-FPGA systems | Lin, T.-W.; Tai, W.-C.; Lin, Y.-C.; HUI-RU JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
2004 | Simultaneous Floorplan and Buffer-Block Optimization | HUI-RU JIANG ; YAO-WEN CHANG ; Jou, Jing-Yang; Chao, Kai-Yuan | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 10 | 2 | |
2003 | Simultaneous floorplanning and buffer block planning. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |
2011 | Simultaneous functional and timing ECO. | Chang, Hua-Yu; Jiang, Iris Hui-Ru; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 17 | 0 | |
2010 | Simultaneous voltage island generation and floorplanning | Li, H.-Y.; Jiang, I.H.-R.; Chen, H.-M.; HUI-RU JIANG | Proceedings - IEEE International SOC Conference, SOCC 2010 | 2 | 0 | |
2024 | Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops | Chen, Yen Yu; Wu, Hao Yu; HUI-RU JIANG ; CHENG-HONG TSAI; Wu, Chien Cheng | Proceedings of the International Symposium on Physical Design | | | |
2015 | Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations | Jiang, I.H.-R.; Nam, G.-J.; Chang, H.-Y.; Nassif, S.R.; Hayes, J.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 7 | 0 | |
2022 | Sub-resolution assist feature generation with reinforcement learning and transfer learning | Liu, Guan Ting; Tai, Wei Chen; Lin, Yi Ting; HUI-RU JIANG ; Shiely, James P.; PU-JEN CHENG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
2021 | Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval | Tseng S.S.-E; Shiely J.P.; HUI-RU JIANG | Proceedings - Design Automation Conference | 2 | 0 | |
2012 | Timing ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
2011 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
2012 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 | |
2018 | Timing Macro Modeling for Efficient Hierarchical Timing Analysis. | Jiang, Iris Hui-Ru; Lee, Pei-Yu; HUI-RU JIANG | 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018 | 0 | 0 | |
2022 | Timing macro modeling with graph neural networks | Chang, Kevin Kai Chun; Chiang, Chun Yao; Lee, Pei Yu; HUI-RU JIANG | Proceedings - Design Automation Conference | 3 | 0 | |