公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2012 | Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs | C.-Y. Hsieh; M.-L. Fan; VITA PI-HO HU | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 40 | 29 | |
2021 | Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors | Gupta M; Hu V.P.-H.; VITA PI-HO HU | ECS Journal of Solid State Science and Technology | 2 | 2 | |
2015 | Investigation and Simulation of Work-Function Variation for III-V Broken-Gap Heterojunction Tunnel FET | C.-W. Hsu; M.-L. Fan; V. P.-H. Hu; Pin Su; VITA PI-HO HU ; C.-W. Hsu; M.-L. Fan; V. P.-H. Hu; Pin Su; 胡璧合 | IEEE Journal of the Electron Devices Society | 20 | 0 | |
2015 | Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET | M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; C.-W. Hsu; Pin Su; C.-T. Chuang; VITA PI-HO HU ; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; C.-W. Hsu; Pin Su; C.-T. Chuang; 胡璧合 | IEEE Transactions on Electron Devices | 24 | 20 | |
2016 | Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs | VITA PI-HO HU ; Su P; Chuang C.-T. | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | 0 | |
2010 | Investigation of cell stability and write ability of finfet subthreshold SRAM using analytical SNM model | Fan M.-L; Wu Y.-S; VITA PI-HO HU ; Su P; Chuang C.-T. | IEEE Transactions on Electron Devices | 33 | 20 | |
2011 | Investigation of Electrostatic Integrity for Ultrathin-Body Germanium-On-Nothing MOSFET | Y.-S. Wu; P. Su; VITA PI-HO HU | IEEE Transactions on Nanotechnology | 11 | 9 | |
2009 | Investigation of static noise margin of ultra-thin-body SOI SRAM cells in subthreshold region using analytical solution of poisson's equation | VITA PI-HO HU ; Wu Y.-S; Fan M.-L; Su P; Chuang C.-T. | International Symposium on VLSI Technology, Systems, and Applications, Proceedings | 0 | 0 | |
2021 | Monolithic 3D SRAM cell with stacked two-dimensional materials based FETs at 2nm node | Su C.-W; Yu C.-C; Liu C.-J; Weng C.-Y.; VITA PI-HO HU | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | 0 | |
2018 | Negative capacitance enables FinFET and FDSOI scaling to 2 nm node | Hu V.P.-H; Chiu P.-C; Sachid A.B; Hu C.; VITA PI-HO HU | Technical Digest - International Electron Devices Meeting, IEDM | 17 | 0 | |
2020 | Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications | M. Gupta; V. P.-H. Hu; VITA PI-HO HU ; M. Gupta; V. P.-H. Hu; 胡璧合 | IEEE Electron Device Letters | 21 | 21 | |
2022 | On the thickness dependence of the polarization switching kinetics in HfO2-based ferroelectric | Sawabe, Yoshiki; Saraya, Takuya; Hiramoto, Toshiro; Su, Chun Jung; VITA PI-HO HU ; Kobayashi, Masaharu | Applied Physics Letters | 5 | 5 | |
2018 | Optimization of III-V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression | C.-T. Wang; VITA PI-HO HU | Japanese Journal of Applied Physics | 12 | 10 | |
2020 | Optimization of Negative-Capacitance Vertical-Tunnel FET(NCVT-FET) | H.-H. Lin; Y.-K. Lin; C. Hu; VITA PI-HO HU | IEEE Transactions on Electron Devices | 49 | 43 | |
2019 | Reduced RTN amplitude and single trap induced variation for ferroelectric FinFET by substrate doping optimization | Lin Z.-T; Hu V.P.-H.; VITA PI-HO HU | 2019 Silicon Nanoelectronics Workshop, SNW 2019 | 1 | 0 | |
2017 | Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell and Sense Amplifier | V. P.-H. Hu; VITA PI-HO HU ; V. P.-H. Hu; 胡璧合 | IEEE Journal of the Electron Devices Society | 8 | 7 | |
2023 | Robust Recovery Scheme for MFIS-FeFETs at Optimal Timing with Prolonged Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit Design | Wu, C. H.; Liu, J.; Zheng, X. T.; Tseng, Y. M.; Kobayashi, M.; VITA PI-HO HU ; Su, C. J. | Technical Digest - International Electron Devices Meeting, IEDM | | | |
2021 | Sensitivity Analysis and Design of Negative-Capacitance Junctionless Transistor for High-Performance Applications | Gupta M; VITA PI-HO HU | IEEE Transactions on Electron Devices | 2 | 2 | |
2022 | Sensitivity Analysis of Ferroelectric Junctionless Transistors for Non-volatile Memory Applications | Gupta M; VITA PI-HO HU | 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022 | 1 | 0 | |
2014 | Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits | M.-L. Fan; S.-Y. Yang; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU | Microelectronics Reliability | 23 | 22 | |