公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1994 | An H-V Alternating Router | Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung | IEEE Transactions on CAD | | | |
1991 | An H-V Tile Expansion Router | Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung | Journal of Information Science and Engineering | | | |
1989 | An H-V Tile-Expansion Router | Tsai, C. C.; 陳少傑 ; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | National Computer Symposium | | | |
1989 | A Heuristic Scanning Line Approach for an Expert Layout Compactor | Hsiao, P. Y.; Chen, S. F. Steven; 馮武雄; Feng, Wu-Shiung | The IFIP VLSI'89 Conference | | | |
1987 | Hierarchical Layout System | Tsai, C. C.; Kuo, S. T.; Uang, T. C.; Wang, L. J.; Yeap, K. H.; 馮武雄; Feng, Wu-Shiung | International Symposium on VLSI Technology, Systems, and Applications, Taipei(1987.05) | | | |
1986 | Hierarchical Placement System for VLSI Design | 馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Hierarchical Timing Verification System for Multiple Clocked Logic Circuit | Tyan, C. Y.; 馮武雄; 于惠中; Yeh, T. S.; Feng, Wu-Shiung; Yu, Hui-Jung | 1986 Electron Devices and Materials Symposium, Tainan(1986.08) | | | |
1985 | Highly Concurrent Algorithm and Pipelined VLSI Architecture for Solving Covariance Systems | Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Yu, Hui-Jung; Feng, Wu-Shiung | International AMSE Conference on Modelling and Simulation Storrs, Connecticut(1985.07.01-07.03) | | | |
1986 | HILAS-an Hierarchical and Interactive Layout Editor System | 馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1987 | HILAS-Hierarchical Interactive Layout System | Tsai, C. C.; 馮武雄; Feng, Wu-Shiung | 1987 Electron Devices and Materials Symposium, Taipei(1987.09) | | | |
1991 | Hybrid Routing on Multi-Chip Modules | Tsai, C. C.; 陳少傑 ; Hsiao, P. Y.; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | 1991 Custom Integrated Circuits Conference | | | |
1992 | An Improved Analytical Model for Short-Channel MOSFET's | Chow, H. C.; 馮武雄; Feng, Wu-Shiung | IEEE Transactions on Electron Devices | | | |
1990 | An Improved Analytical Model of Short Channel MOSFETs Suitable for Circuit Simulation | Chow, H. C.; Wang, J. H.; Kuo, J, B.; 馮武雄; Feng, Wu-Shiung | The 2nd Workshop on CAD for VLSI | | | |
1993 | An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digital Circuit Si[20642:0:4] 50300022:31:An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digit | Chow, H. C.; 馮武雄; Kuo, J. B.; Feng, Wu-Shiung | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
1989 | An Improved Control Strategy for Expert Compaction Design | Hsiao, P. Y.; Chen, H. F.; 馮武雄; Chen, S. J.; Tsai, C. C.; Feng, Wu-Shiung | The IASTED International Symposium Expert Systems Theory & Applications, Zurich, Switzerland(1989.06.26-06.28) | | | |
1989 | An Improved Control Strategy for Expert Layout Compaction Design | Hsiao, P. Y.; Chen, H. F.; 馮武雄; 陳少傑 ; Tsai, C. C.; Feng, Wu-Shiung; Chen, Sao-Jie | 1989 International Symposium on Expert Systems Theory & Applications | | | |
1988 | An Incremental Design Rule Checking Based on Quad Tree Representations | Hsiao, P. Y.; 馮武雄; Feng, Wu-Shiung | ISMM International Symposium Mini and Microcomputers, Florida(1988.12.14) | | | |
1986 | Integrated Entry and Verification System | Yuan, Y. C.; 馮武雄; 龐台銘; Feng, Wu-Shiung; Parng, Tai-Ming | Proceedings of International Computer Symposium | | | |
1986 | Integrated Entry and Verification System for VLSI Design | 馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1986 | Integrated VLSI Design System - Main System Design | Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |