公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2004 | Temporal floorplanning using the T-tree formulation | Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 62 | | |
2002 | The C-terminal domain of the largest subunit of RNA polymerase II is required for stationary phase entry and functionally interacts with the Ras/PKA signaling pathway | Howard, S. C.; YA-WEN CHANG ; Budovskaya, Y. V.; Chang, Y.-W.; Herman, P. K. | Journal of Biological Chemistry | 23 | 22 | |
2004 | The Ras/PKA signaling pathway directly targets the Srb9 protein, a component of the general RNA polymerase II transcription apparatus | Chang, Y.-W.; YA-WEN CHANG ; Howard, S. C.; Herman, P. K. | Molecular Cell | 62 | 62 | |
2014 | Theory of charge transport in molecular junctions: From Coulomb blockade to coherent tunneling | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Journal of Chemical Physics | 4 | 4 | |
2017 | Theory of charge transport in molecular junctions: Role of electron correlation | Chang, Y.-W.; BIH-YAW JIN ; YAO-WEN CHANG | Journal of Chemical Physics | 2 | 2 | |
2011 | Thermal-driven analog placement considering device matching | Lin, M.P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 26 | 20 | |
2009 | Thermal-driven analog placement considering device matching | Lin, P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 26 | | |
2007 | Thermal-driven interconnect optimization by simultaneous gate and wire sizing | Lin, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG | 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 | 0 | 0 | |
2009 | Thermoelectric air-cooling module for electronic devices | Chang, Y.-W.; Chang, C.-C.; Ke, M.-T.; SIH-LI CHEN | Applied Thermal Engineering | 120 | 98 | |
2010 | Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis | Falkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 55 | 0 | |
2012 | TRECO: Dynamic technology remapping for timing engineering change orders | Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 8 | |
2013 | TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model | Hsu, M.-K.; Balabanov, V.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 68 | 54 | |
2011 | TSV-aware analytical placement for 3D IC designs | Hsu, M.-K.; Chang, Y.-W.; Balabanov, V.; YAO-WEN CHANG | Design Automation Conference | 77 | | |
2010 | Unified analytical global placement for large-scale mixed-size circuit designs | Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 8 | 0 | |
2012 | Unified analytical global placement for large-scale mixed-size circuit designs | Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 19 | |
2004 | Universal switch blocks for three-dimensional FPGA design | Wu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG | IEE Proceedings: Circuits, Devices and Systems | 9 | 7 | |
2004 | Universal switch blocks for three-dimensional FPGA design | Wu, G.-M.; Shyu, M.; Chang, Y.-W. | IEE Proceedings-Circuits | | | |
2016 | VCR: Simultaneous via-template and cut-template-aware routing for directed self-assembly technology | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 4 | 0 | |
2006 | Voltage Island aware floorplanning for power and timing optimization | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 74 | 0 | |
2011 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 3 | |