公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2016 | VCR: Simultaneous via-template and cut-template-aware routing for directed self-assembly technology | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 4 | 0 | |
2006 | Voltage Island aware floorplanning for power and timing optimization | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 74 | 0 | |
2011 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 3 | |
2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 4 | | |
2009 | Voltage-island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 11 | |
2009 | Voltage-Island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 11 | |
2007 | Word-level parallel architecture of JPEG 2000 embedded block coding decoder | Chang, Y.-W.; Fang, H.-C.; Chen, C.-C.; Lian, C.-J.; Chen, L.-G.; LIANG-GEE CHEN | IEEE Transactions on Multimedia | 3 | 3 | |
2007 | X-architecture placement based on effective wire models | Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 1 | 0 | |
2007 | X-route: An x-architecture full-chip multilevel router | Chang, C.-F.; Chang, Y.-W.; YAO-WEN CHANG | 20th Anniversary IEEE International SOC Conference | 4 | 0 | |