| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2019 | Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. | Alioto, Massimo; Abadir, Magdy S.; Arslan, Tughrul; Boon, Chirn Chye; Burg, Andreas; Chang, Chip-Hong; Chang, Meng-Fan; Chang, Yao-Wen; Chen, Poki; Corsonello, Pasquale; Crovetti, Paolo; Dosho, Shiro; Drechsler, Rolf; Elfadel, Ibrahim Abe M.; Han, Ruonan; Hashimoto, Masanori; Heng, Chun-Huat; Heo, Deukhyoun; Ho, Tsung-Yi; Homayoun, Houman; Hwang, Yuh-Shyan; Joshi, Ajay; Joshi, Rajiv V.; Karnik, Tanay; Kim, Chulwoo; Kim, Tae-Hyoung; Kulkarni, Jaydeep; Kursun, Volkan; Lee, Yoonmyung; Li, Hai Helen; Li, Huawei; Mishra, Prabhat; Mohammad, Baker; Kermani, Mehran Mozaffari; Nagata, Makoto; Nii, Koji; Pande, Partha Pratim; Paul, Bipul C.; Pavlidis, Vasilis F.; Gyvez, Jos? Pineda de; Savidis, Ioannis; Schaumont, Patrick; Sebastiano, Fabio; Sengupta, Anirban; Seok, Mingoo; Stan, Mircea R.; Tehranipoor, Mark M.; Todri-Sanial, Aida; Verhelst, Marian; Vignoli, Valerio; Wen, Xiaoqing; Xu, Jiang; Zhang, Wei; Zhang, Zhengya; Zhou, Jun; Zwolinski, Mark; Weber, Stacey; YAO-WEN CHANG | IEEE Trans. VLSI Syst. | 4 | 4 | |
| 2017 | Editorial. | Chakrabarty, Krishnendu; Alioto, Massimo; Baas, Bevan M.; Boon, Chirn Chye; Chang, Meng-Fan; Chang, Naehyuck; Chang, Yao-Wen; Chang, Chip-Hong; Chang, Shih-Chieh; Chen, Poki; Chowdhury, Masud H.; Corsonello, Pasquale; Elfadel, Ibrahim Abe M.; Hamdioui, Said; Hashimoto, Masanori; Ho, Tsung-Yi; Homayoun, Houman; Hwang, Yuh-Shyan; Joshi, Rajiv V.; Karnik, Tanay; Kermani, Mehran Mozaffari; Kim, Chulwoo; Kim, Tae-Hyoung; Kulkarni, Jaydeep P.; Kursun, Eren; Larsson, Erik; Li, Hai (Helen); Li, Huawei; Mercier, Patrick P.; Mishra, Prabhat; Nagata, Makoto; Natarajan, Arun S.; Nii, Koji; Pande, Partha Pratim; Savidis, Ioannis; Seok, Mingoo; Tan, Sheldon X.-D.; Tehranipoor, Mark Mohammad; Todri-Sanial, Aida; Velev, Miroslav N.; Wen, Xiaoqing; Xu, Jiang; Zhang, Wei; Zhang, Zhengya; Jackson, Stacey Weber; YAO-WEN CHANG | IEEE Trans. VLSI Syst. | 0 | 0 | |
| 2008 | An efficient graph-based algorithm for ESD current path analysis | Liu, Chih-Hung; Liu, Hung-Yi; Lin, Chung-Wei; Chou, Szu-Jui; Chang, Yao-Wen; Kuo, Sy-Yen; Yuan, Shih-Yi; Chen, Yu-Wei; CHUNG-WEI LIN | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 2 | |
| 2007 | Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. | Lin, Chung-Wei; Huang, Shih-Lun; Hsu, Kai-Chi; Li, Meng-Xiang; Chang, Yao-Wen; CHUNG-WEI LIN | 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007 | 14 | 0 | |
| 2007 | Efficient obstacle-avoiding rectilinear steiner tree construction. | Lin, Chung-Wei; Chen, Szu-Yu; Li, Chi-Feng; Chang, Yao-Wen; Yang, Chia-Lin; CHUNG-WEI LIN | Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007 | 35 | 0 | |
| 2007 | Efficient obstacle-avoiding rectilinear steiner tree construction. | Lin, Chung-Wei; Chen, Szu-Yu; Li, Chi-Feng; Chang, Yao-Wen; Yang, Chia-Lin; CHIA-LIN YANG | Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007 | 35 | 0 | |
| 2004 | Efficient power/ground network analysis for power integrity-driven design methodology. | Wu, Su-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004 | 21 | 0 | |
| 2012 | An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs | Lin, Chung-Wei; Lee, Po-Wei; Chang, Yao-Wen; Shen, Chin-Fang; Tseng, Wei-Chih; CHUNG-WEI LIN | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 8 | |
| 2009 | An efficient pre-assignment routing algorithm for flip-chip designs. | Lee, Po-Wei; Lin, Chung-Wei; Chang, Yao-Wen; Shen, Chin-Fang; Tseng, Wei-Chih; CHUNG-WEI LIN | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 15 | 0 | |
| 2009 | An efficient pre-assignment routing algorithm for flip-chip designs. | Lee, Po-Wei; Lin, Chung-Wei; Chang, Yao-Wen; Shen, Chin-Fang; Tseng, Wei-Chih; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 15 | 0 | |
| 2010 | Efficient provably good OPC modeling and its applications to interconnect optimization. | Huang, Shih-Lun; Lin, Chung-Wei; Chang, Yao-Wen; CHUNG-WEI LIN | 28th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings | 0 | 0 | |
| 2005 | An exact jumper insertion algorithm for antenna effect avoidance/fixing. | Su, Bor-Yiing; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005 | 11 | 0 | |
| 1996 | Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG | Design Automation Conference | 24 | | |
| 1996 | Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. | Chen, Chung-Ping; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG | Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996. | 24 | 0 | |
| 2009 | Flip-chip routing with unified area-I/O pad assignments for package-board co-design. | Fang, Jia-Wei; Wong, Martin D. F.; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | 32 | 0 | |
| 2006 | Floorplan and power/ground network co-synthesis for fast design convergence. | Liu, Chen-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 22 | 0 | |
| 2002 | Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. | Chang, Nicholas Chia-Yuan; Chang, Yao-Wen; Jiang, Iris Hui-Ru; HUI-RU JIANG | 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002 | 1 | 0 | |
| 1995 | FPGA global routing based on a new congestion metric | Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 13 | | |
| 1995 | FPGA global routing based on a new congestion metric. | Chang, Yao-Wen; Wong, D. F.; Wong, C. K.; YAO-WEN CHANG | 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings | 0 | 0 | |
| 2007 | Full-Chip Nanometer Routing Techniques. | Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; YAO-WEN CHANG | | | | |
