公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1995 | Efficient approach for via minimization in multi-layer VLSI/PCB routing | Cherng, Jong-Sheng; Chen, Sao-Jie; Tsai, Chia-Chun; Ho, Jan-Ming; SAO-JIE CHEN | Custom Integrated Circuits Conference | | | |
2000 | Efficient routability check algorithms for segmented channel routing | Yang, Cheng-Hsing; Chen, Sao-Jie; Ho, Jan-Ming; Tsai, Chia-Chun | ACM Transactions on Design Automation of Electronic Systems | | | |
1993 | Efficient signal redistribution algorithm for MCM | Shiao, Ming-Fu; Changfan, Chieh; Chen, Sao-Jie; Tsai, Chia-Chun; SAO-JIE CHEN | Custom Integrated Circuits Conference | | | |
1999 | Even wiring approach to the ball grid array package routing | Chen, Shuenn-Shi; Chen, Jong-Jang; Tsai, Chia-Chun; Chen, Sao-Jie; SAO-JIE CHEN | IEEE International Conference on Computer Design: VLSI in Computers and Processors | | | |
2009 | Evolution and integration of medical laboratory information system in an Asia national medical center | Cheng, Po-Hsun; Chen, Sao-Jie; Lai, Jin-Shin; Cheng, Po-Hsun; Chen, Sao-Jie; Lai, Jin-Shin; JIN-SHIN LAI ; SAO-JIE CHEN ; 鄭伯壎 | IEICE Transactions on Communications | 2 | 1 | |
2007 | Full-Chip Nanometer Routing Techniques. | Ho, Tsung-Yi; Chang, Yao-Wen; Chen, Sao-Jie; YAO-WEN CHANG | | | | |
1990 | A General Area Router Based on Planning Techniques | 陳少傑; Tsai, C. C.; Chen, Y. L.; Hu, Y. H.; Chen, Sao-Jie | IEEE Proceedings. E, Computers and digital techniques | | | |
1990 | GM_Learn:an Iterative Learning Algorithm for CMOS Gate Matrix Layout | 陳少傑; Hu, Y. H.; Chen, Sao-Jie | IEEE Proceedings. E, Computers and digital techniques | | | |
1990 | GM_Plan:A Gate Matrix Layout Algorithm Based on AI Planning Techniques | Hu, Y. H.; 陳少傑; Chen, Sao-Jie | IEEE Transactions on CAD | | | |
1994 | An H-V Alternating Router | Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung | IEEE Transactions on CAD | | | |
1991 | An H-V Tile Expansion Router | Tsai, C. C.; 陳少傑; 馮武雄; Chen, Sao-Jie; Feng, Wu-Shiung | Journal of Information Science and Engineering | | | |
2009 | Hardware software co-design of a multimedia SOC platform | Hu, Yu-Hen; Hsiung, Pao-Ann; Lin, Guang-Huei; Chen, Sao-Jie | | 0 | 0 | |
2001 | Hardware-Software Multi-Level Partitioning for Distributed Embedded Multiprocessor Systems | Lee, Trong-Yen; Hsiung, Pao-Ann; Chen, Sao-Jie | IEICE TRANSACTIONS on Fundamentals of Electronics | | | |
2000 | Hardware-Software Timing Coverification of Distributed Embedded Systems | Fu, Jih-Ming; Lee, Trong-Yen; Hsiung, Pao-Ann; Chen, Sao-Jie | IEICE TRANSACTIONS on Information and Systems E83-D | | | |
2004 | Home Telehealth: Bring Care to the Point of Living | CHEN, CHIA-HUI; SU, MEI-JU; HWANG, SHIOW-LI; CHEN, SAO-JIE; DAI, YU-TZU; CHEN, HENG-SHUEN; 陳佳慧; 蘇美如; 黃秀梨; 陳少傑; 戴玉慈; 陳恆順 | 台灣醫學,v.8 | | | |
2002 | IETQ: An Incrementally Extensible Twisted Cube | Chang, Jyh-Shan; Chen, Sao-Jie; Chiueh, Tzi-Dar | IEICE Transactions on Fundamentals of Electronics | 0 | 0 | |
1999 | Improved Pyramid algorithm for synthesizing 2-D discrete wavelet transforms | Yu, Chu; Chen, Sao-Jie; SAO-JIE CHEN | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
1993 | Iterative Planning:a Scheme for VLSI Physical Design Problem | Chen, Sao-Jie | Proceedings of the National Science Council (Republci of China). Part A | | | |
1994 | Layout Compaction Based on Alternating Routing | Chen, Sao-Jie | Bulletin of the College of Engineering | | | |
1994 | A Linear Time Algorithm for Planar Moat Routing | Tsai, C. C.; 陳少傑; Chen, Sao-Jie | Journal of Information Science and Engineering | | | |