公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
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2004 | Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection | Hsiang-Hui Chang; Rong-Jyi Yang; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 12 |