公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1990 | A General Area Router Based on Planning Techniques | 陳少傑; Tsai, C. C.; Chen, Y. L.; Hu, Y. H.; Chen, Sao-Jie | IEEE Proceedings. E, Computers and digital techniques | | | |
1989 | GM-Learn:an Iterative Learning Algorithm for CMOS Gate Matrix Layout | 陳少傑 ; Hu, Y. H.; Chen, Sao-Jie | 1989 International Symposium on Circuits and Systems | | | |
1990 | GM_Learn:an Iterative Learning Algorithm for CMOS Gate Matrix Layout | 陳少傑; Hu, Y. H.; Chen, Sao-Jie | IEEE Proceedings. E, Computers and digital techniques | | | |
1990 | GM_Plan:A Gate Matrix Layout Algorithm Based on AI Planning Techniques | Hu, Y. H.; 陳少傑; Chen, Sao-Jie | IEEE Transactions on CAD | | | |
1985 | Highly Concurrent Algorithm and Pipelined VLSI Architecture for Solving Covariance Systems | Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Yu, Hui-Jung; Feng, Wu-Shiung | International AMSE Conference on Modelling and Simulation Storrs, Connecticut(1985.07.01-07.03) | | | |
1986 | Lattice Filter Array Implementation of Pipelined Toeplitz System Solver | Jou, I. C.; Hu, Y. H.; 馮武雄; Feng, Wu-Shiung | 1986 IEEE International Symposium on Circuits and Systems, San Jose, CA(1986.05) | | | |
1989 | A Novel Implementation of Pipelined Toeplitz System Solver | Jou, I. C.; Hu, Y. H.; 馮武雄; Feng, Wu-Shiung | Proceeding of IEEE | | | |
1986 | Parallel Algorithm and Architecture for Solving Covariance Eigen System | Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Yu, Hui-Jung; Feng, Wu-Shiung | Advances in Modelling and Simulation, France | | | |
1992 | Planning Strategies for Area Routing | Tsai, C. C.; 陳少傑 ; Chen, Y. L.; Hu, Y. H.; Chen, Sao-Jie | 1992 European Conference on Design Automation | | | |
1990 | The Production of Foie Gras in Mule Ducks | Chen, M. C.; Hu, Y. H.; Pan, C. M.; 陳保基 ; Chen, Bao-Ji | Proceedings of the 5th AAAP Animal Science Congress | | | |