公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2009 | Logic and Circuit Simulation | Huang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG | Electronic Design Automation | 2 | 0 | |
2009 | Logic and Circuit Simulation | Huang, J.-L.; Koh, C.-K.; Cauley, S. F. | in book:Electronic Design Automation: Synthesis | | | |
2006 | Logic and Fault Simulation | Huang, J.-L.; Li, James C.-M.; Walker, Duncan M. (Hank) | VLSI Test | | | |
2008 | Mining top-k frequent patterns in the presence of the memory constraint | Chuang, K.-T.; Huang, J.-L.; Chen, M.-S.; MING-SYAN CHEN | VLDB Journal | 55 | 39 | |
2019 | A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction | Li, B.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - International SoC Design Conference 2018, ISOCC 2018 | 0 | 0 | |
2006 | On exploring the power-law relationship in the itemset support distribution | Chuang, K.-T.; Huang, J.-L.; Chen, M.-S.; MING-SYAN CHEN | Lecture Notes in Computer Science | 2 | 1 | |
2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
2011 | On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imager | Huang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 1 | 0 | |
2008 | Power-law relationship and self-similarity in the itemset support distribution: Analysis and applications | Chuang, K.-T.; Huang, J.-L.; Chen, M.-S.; MING-SYAN CHEN | VLDB Journal | 13 | 10 | |
2019 | Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test | Chen, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 9 | 0 | |
2010 | A robust ADC code hit counting technique | Huang, J.-L.; Chou, K.-Y.; Lu, M.-H.; Huang, X.-L.; JIUN-LANG HUANG | Proceedings -Design, Automation and Test in Europe, DATE | 1 | | |
2006 | Scheduling dependent items in data broadcasting environments | Hung, H.-P.; Huang, J.-W.; Huang, J.-L.; Chen, M.-S.; MING-SYAN CHEN | ACM Symposium on Applied Computing | 16 | | |
2008 | Software-Based Self-Testing | Huang, J.-L.; Tim, K.-T.; JIUN-LANG HUANG | System-on-Chip Test Architectures | 0 | 0 | |
2007 | Software-Based Self-Testing | Huang, J.-L.; Cheng, K.-T. | in book:System on Chip Test Architectures, Chap. 11 | | | |
2011 | Structural and optical properties of InGaN/GaN multiple quantum well light emitting diodes grown on (1122) facet GaN/sapphire templates by metalorganic chemical vapor deposition | Huang, J.-L.; Wang, L.S.; Lai, Y.-S.; Lee, Y.-C.; Qiu, Z.R.; Liu, S.; Wuu, D.-S.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | 1 | 0 | |
2000 | Test point selection for analog fault diagnosis of unpowered circuit boards | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 18 | 16 | |
2012 | Testing and calibration of SAR ADCs by MCT-based bit weight extraction | Huang, X.-L.; Chen, H.-I.; Huang, J.-L.; Chen, C.-Y.; Kuo-Tsai, T.; Huang, M.-F.; Chou, Y.-F.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | 7 | 0 | |
2012 | Time-resolved and temperature-varied photoluminescence studies of InGaN/GaN multiple quantum well structures | Liu, L.; Wang, W.; Huang, J.-L.; Hu, X.; Chen, P.; Huang, J.-J.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | 4 | 0 | |
2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 | |
2012 | Welcome message | Wu, C.-W.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | 0 | 0 | |