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J. B. Kuo
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公開日期
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作者
來源出版物
scopus
WOS
全文
2014
A Surface-Field-Based Model for Nanowire MOSFETs with Spatial Variations of Doping Profiles
Q. Cheng; C. Y. Hong; J. B. Kuo; Y. J. Chen; JAMES-B KUO
IEEE Transactions on Electron Devices
16
17
2006
Analysis of Fringing Electric Field Related Capacitance Behavior of Narrow-Channel FD SOI NMOS Devices Using 3D Simulation
C. C. Chen; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO
ICSICT
0
0
2003
Analysis of Gate Misalignment Effect on the Threshold Voltage of Double-Gate (DG) Ultrathin FD SOI NMOS Devices Using a Compact Model Considering Fringing Electric Field Effect
J. B. Kuo; E. C. Sun; M. T. Lin; JAMES-B KUO
IEEE Electron Devices for Microwave and Optoelectronic Applications
0
0
2015
Analysis of Subthreshold Behavior of SOI NMOS De ice Considering Back-Gate-Bias-Related Flaoting Body Effect
S. K. Hu; J. B. Kuo; JAMES-B KUO
Workshop on Microelectronics and Electron Devices (WMED)
2006
Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOINMOS device considering the 3-D fringing capacitances using 3-D simulation
C. C. Chen; J. B. Kuo; K. W. Su,; S. Liu; JAMES-B KUO
IEEE Transactions on Electron Devices
3
2
2011
Analysis of Turn-off Transient Behavior of the 40nm PD SOI NMOS Device with the Floating Body Effect
C. H. Chen; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
International Electron Device Material Symposium
2013
Analytical Drain Current Model for Poly-Si Thin-Film Transistors Biased in Strong Inversion Considering Degradation of Tail States at Grain Boundary
L. L. Wang; J. B. Kuo; S. Zhang; JAMES-B KUO
IEEE Transactions on Electron Devices
0
0
2003
Asymmetric Gate Misalignment Effect on Subthreshold Characteristics DG SOI NMOS Devices Considering Fringing Electric Field Effect
M. T. Lin; E. C. Sun; J. B. Kuo; JAMES-B KUO
Electron Devices and Material Symposium
2013
Back-Gate Bias Effect of PD SOI NMOS Device Considering BJT
D. H. Lung; J. B. Kuo; JAMES-B KUO
International Conference on EECS
2014
Back-Gate-Baias Induced Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device
S. K. Hu; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
IEDMS
2011
Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique
S. F. Huang; R. S. Shen; J. B. Kuo; JAMES-B KUO
Power and Timing Modeling Optimization Symposium
2
0
2005
CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects
Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO
HKEDSSC
0
0
2010
Charge Pumping Behavior of STI-Isolated PD SOI NMOS Device Operating at Low Temp
C. F. Yen; J. B. Kuo; JAMES-B KUO
IEDMS
2002
Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion
S. C. Lin; J. B. Kuo; JAMES-B KUO
IEEE Transactions on Electron Devices
3
1
2009
Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide
C. H. Lin; J. B. Kuo; JAMES-B KUO
Solid State Electronics
1
1
1998
CMOS VLSI Engineering: Silicon-on-Insulator (SOI)
J. B. Kuo; K. W. Su; JAMES-B KUO
2002
Compact Breakdown Model for PD SOI NMOS Devices Considering BJT/MOS Impact Ionization for SPICE Circuits Simulation
J. B. Kuo; S. C. Lin; JAMES-B KUO
IEDMS
2006
Compact Gate Tunneling Current Model Considering Distributed Effect for Sub-100nm NMOS Devices with Ultra-thin (1nm) Gate Oxide
C. H. Lin; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO
IEDMS
2002
Compact LDD/FD SOI CMOS Device Model Considering Energy Transport and Self Heating for SPICE Circuit Simulation
J. B. Kuo; S. C. Lin; JAMES-B KUO
IEDMS
1999
Compact MOS/Bipolar Charge-Control Model of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation---SOI-Technology (ST)-SPICE
J. B. Kuo; K. W. Su; S. C. Lin; JAMES-B KUO
European Solid State Device Research Conference (ESSDERC)