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J. B. Kuo
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作者
來源出版物
scopus
WOS
全文
2013
Back-Gate Bias Effect of PD SOI NMOS Device Considering BJT
D. H. Lung; J. B. Kuo; JAMES-B KUO
International Conference on EECS
2014
Back-Gate-Baias Induced Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device
S. K. Hu; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
IEDMS
1999
Bandgap Narrowing
J. B. Kuo; JAMES-B KUO
Wiley Encyclopedia on Electrical Engineering
2006
Capacitance Behavior of Nanometer FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Gate Tunneling Leakage Current
J. B. Kuo; JAMES-B KUO
MIEL
2
0
2011
Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique
S. F. Huang; R. S. Shen; J. B. Kuo; JAMES-B KUO
Power and Timing Modeling Optimization Symposium
2
0
2005
CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects
Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO
HKEDSSC
0
0
2010
Charge Pumping Behavior of STI-Isolated PD SOI NMOS Device Operating at Low Temp
C. F. Yen; J. B. Kuo; JAMES-B KUO
IEDMS
2002
Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion
S. C. Lin; J. B. Kuo; JAMES-B KUO
IEEE Transactions on Electron Devices
3
1
2009
Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide
C. H. Lin; J. B. Kuo; JAMES-B KUO
Solid State Electronics
1
1
2004
CMOS Digital IC
J. B. Kuo; JAMES-B KUO
1998
CMOS VLSI Engineering: Silicon-on-Insulator (SOI)
J. B. Kuo; K. W. Su; JAMES-B KUO
2002
Compact Breakdown Model for PD SOI NMOS Devices Considering BJT/MOS Impact Ionization for SPICE Circuits Simulation
J. B. Kuo; S. C. Lin; JAMES-B KUO
IEDMS
2006
Compact Gate Tunneling Current Model Considering Distributed Effect for Sub-100nm NMOS Devices with Ultra-thin (1nm) Gate Oxide
C. H. Lin; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO
IEDMS
2002
Compact LDD/FD SOI CMOS Device Model Considering Energy Transport and Self Heating for SPICE Circuit Simulation
J. B. Kuo; S. C. Lin; JAMES-B KUO
IEDMS
2009
Compact Modelign of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation
J. B. Kuo; JAMES-B KUO
NSC Seminar
2014
Compact Modeling of 40nm Pd SOI NMOS Devices Considering Floating Body Effect
J. B. Kuo; JAMES-B KUO
MOST Microelectronics Research Seminar
2011
Compact Modeling of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation
J. B. Kuo; JAMES-B KUO
NSC Seminar
2012
Compact Modeling of SOI CMOS Devices
J. B. Kuo; JAMES-B KUO
NSC Seminar
2008
Compact Modeling of Sub-90nm CMOS VLSI Devices Considering Fringing Electric Field Effects
J. B. Kuo; JAMES-B KUO
NSC Seminar
1999
Compact MOS/Bipolar Charge-Control Model of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation---SOI-Technology (ST)-SPICE
J. B. Kuo; K. W. Su; S. C. Lin; JAMES-B KUO
European Solid State Device Research Conference (ESSDERC)