公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2008 | Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signals, Sensors, and Systems Test Workshop | 6 | 0 | |
2009 | Ch. 8 Logic and Circuit Simulation | J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG | Electronic Design Automation: Synthesis, Verification, and Test | |||
2007 | Chap. 11 Software-Based Self-Testing | J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | System on Chip Test Architectures | |||
2006 | Chap. 3: Logic and Fault Simulation | J.-L. Huang; James C.-M. Li; Duncan M. (Hank) Walker; JIUN-LANG HUANG | VLSI Test Principles and Architectures | |||
2009 | Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automatic Conference | |||
2011 | Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing | Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG | International Test Conference | 3 | 0 | |
2016 | CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator | K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 1 | 1 | |
2017 | Design and implementation of an EG-pool based FPGA formatter with temperature compensation | Y.-K. Huang; K.-T. Li; C.-L. Hsiao; C.-A. Lee; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
2008 | Design of a Fault Tolerant Carry Lookahead Adder | C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG | International Test Synthesis Workshop | |||
2013 | Fault Scrambling Techniques for Yield Enhancement of Embedded Memories | S.-K. Lu; H.-C. Jheng; M. Hashizume; J.-L. Huang; P. Ning; JIUN-LANG HUANG | Asian Test Symposium | 5 | 0 | |
2014 | FPGA-Based Subset Sum Delay Lines | C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2013 | Implementation of programmable delay lines on off-the-shelf FPGAs | Y.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | IEEE AUTOTESTCON | 8 | 0 | |
2013 | Improve speed path identification with suspect path expressions | J.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 0 | 0 | |
2016 | An IR-drop aware test pattern generator for scan-based at-speed testing | P.-F. Hou; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
2016 | An IR-drop guided test pattern generation technique | L.-C. Tsai; J.-Z. Li; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation and Test | 4 | 0 | |
2009 | LPTest: A Flexible Low-Power Test Pattern Generator | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 7 | 5 | |
2016 | A multi-channel FPGA-based time-to-digital converter | L.-Y. Hsu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signal Testing Workshop | 1 | 0 | |
2013 | On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression | K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG | International Conference on VLSI Design | 5 | 0 | |
2008 | PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment | Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 |