公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2017 | Design and implementation of an EG-pool based FPGA formatter with temperature compensation | Y.-K. Huang; K.-T. Li; C.-L. Hsiao; C.-A. Lee; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
2008 | Design of a Fault Tolerant Carry Lookahead Adder | C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG | International Test Synthesis Workshop | |||
2013 | Fault Scrambling Techniques for Yield Enhancement of Embedded Memories | S.-K. Lu; H.-C. Jheng; M. Hashizume; J.-L. Huang; P. Ning; JIUN-LANG HUANG | Asian Test Symposium | 5 | 0 | |
2014 | FPGA-Based Subset Sum Delay Lines | C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2013 | Implementation of programmable delay lines on off-the-shelf FPGAs | Y.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | IEEE AUTOTESTCON | 8 | 0 | |
2013 | Improve speed path identification with suspect path expressions | J.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 0 | 0 | |
2016 | An IR-drop aware test pattern generator for scan-based at-speed testing | P.-F. Hou; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
2016 | An IR-drop guided test pattern generation technique | L.-C. Tsai; J.-Z. Li; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation and Test | 4 | 0 | |
2009 | LPTest: A Flexible Low-Power Test Pattern Generator | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 7 | 5 | |
2016 | A multi-channel FPGA-based time-to-digital converter | L.-Y. Hsu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signal Testing Workshop | 1 | 0 | |
2013 | On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression | K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG | International Conference on VLSI Design | 5 | 0 | |
2008 | PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment | Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
2009 | Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | IEEE Transactions on Compuuter-Aided Design | 16 | 9 | |
2010 | Power supply noise reduction in broadcast-based compression environment for at-speed scan testing | C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2012 | Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications | Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | |||
2008 | Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | International Test Conference | 48 | 0 | |
2011 | Robust Circuit Design for Flexible Electronics | T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | IEEE Design & Test of Computers | 13 | 10 | |
2015 | SDC-TPG: A deterministic zero-inflation parallel test pattern generator | C.-H. Chang; K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2011 | Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs | W.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG | VLSI Test Symposium | 1 | 0 |