公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2013 | On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression | K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG | International Conference on VLSI Design | 5 | 0 | |
2008 | PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment | Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
2009 | Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | IEEE Transactions on Compuuter-Aided Design | 16 | 9 | |
2010 | Power supply noise reduction in broadcast-based compression environment for at-speed scan testing | C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2012 | Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications | Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | |||
2005 | Random jitter testing using low tap-count delay lines | J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 0 | 0 | |
2008 | Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | International Test Conference | 48 | 0 | |
2011 | Robust Circuit Design for Flexible Electronics | T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | IEEE Design & Test of Computers | 13 | 10 | |
2015 | SDC-TPG: A deterministic zero-inflation parallel test pattern generator | C.-H. Chang; K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2011 | Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs | W.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG | VLSI Test Symposium | 1 | 0 | |
2017 | Source code transformation for software-based on-line error detection | T.-Y. Tsai; J.-L. Huang; JIUN-LANG HUANG | IEEE Conference on Dependable and Secure Computing | 3 | 0 | |
2015 | A static bidirectional learning technique to accelerate test pattern generation | J.-H. Pan; K.-W. Yeh; J.-L. Huang; JIUN-LANG HUANG | International SoC Design Conference | 0 | 0 | |
2013 | Synergistic reliability and yield enhancement techniques for embedded SRAMs | S.-K. Lu; H.-H. Huang; J.-L. Huang; P. Ning; JIUN-LANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 8 | |
2008 | Testing LCD Source Driver IC with Built-On-Scribe-Line Test Circuitry | J.-J. Huang; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 |