公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2011 | INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs | Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, L.S.-F.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | 22 | 0 | |
2012 | INTEGRA: Fast multibit flip-flop clustering for clock power saving | Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 42 | 34 | |
2016 | ITimerC 2.0: Fast incremental timing and CPPR analysis | Lee, P.-Y.; Jiang, I.H.-R.; Li, C.-R.; Chiu, W.-L.; Yang, Y.-M.; HUI-RU JIANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | 17 | 0 | |
2015 | ITimerC: Common path pessimism removal using effective reduction methods | Yang, Y.-M.; Chang, Y.-W.; Jiang, I.H.-R.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 15 | 0 | |
2017 | iTimerM: Compact and accurate timing macro modeling for efficient hierarchical timing analysis | Lee, P.-Y.; Jiang, I.H.-R.; Yang, T.-Y.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | 4 | 0 | |
2010 | Live demo: ECOS 1.0: A metal-only ECO synthesizer | Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | 0 | 0 | |
2015 | Machine-learning-based hotspot detection using topological classification and critical feature extraction | Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 77 | 64 | |
2013 | Machine-learning-based hotspot detection using topological classification and critical feature extraction | Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG | Proceedings - Design Automation Conference | 42 | 0 | |
2016 | Multiple patterning layout decomposition considering complex coloring rules | Chang, H.-Y.; Jiang, I.H.-R.; HUI-RU JIANG | Proceedings - Design Automation Conference | 18 | 0 | |
2012 | Novel pulsed-latch replacement based on time borrowing and spiral clustering | Chang, C.-L.; Jiang, I.H.-R.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, A.S.-H.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | 6 | 0 | |
2016 | OpenDesign flow database: The infrastructure for VLSI design and design automation research | Jung, J.; Jiang, I.H.-R.; Nam, G.-J.; Kravets, V.N.; Behjat, L.; Li, Y.-L.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 13 | 0 | |
2019 | Openmpl: An open source layout decomposer: Invited paper | Li, W.; Ma, Y.; Sun, Q.; Lin, Y.; Jiang, I.H.-R.; Yu, B.; Pan, D.Z.; HUI-RU JIANG | Proceedings of International Conference on ASIC | 1 | 0 | |
2010 | Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles | Jiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | 11 | 0 | |
2016 | OWARU: Free space-aware timing-driven incremental placement | Jung, J.; Nam, G.-J.; Reddy, L.; Jiang, I.H.-R.; Shin, Y.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 4 | 0 | |
2009 | POSA: Power-state-aware buffered tree construction | Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG | Proceedings - IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2008 | Power-state-aware buffered tree construction | Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG | 26th IEEE International Conference on Computer Design 2008, ICCD | 3 | 0 | |
2013 | Pulsed-latch replacement using concurrent time borrowing and clock gating | Chang, C.-L.; Jiang, I.H.-R.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 8 | |
2013 | PushPull: Short path padding for timing error resilient circuits | Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | 3 | 0 | |
2014 | PushPull: Short-path padding for timing error resilient circuits | Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 13 | |
2018 | Recent research and challenges in multiple patterning layout decomposition | Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI | 0 | 0 | |