公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2016 | OpenDesign flow database: The infrastructure for VLSI design and design automation research | Jung, J.; Jiang, I.H.-R.; Nam, G.-J.; Kravets, V.N.; Behjat, L.; Li, Y.-L.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2019 | Openmpl: An open source layout decomposer: Invited paper | Li, W.; Ma, Y.; Sun, Q.; Lin, Y.; Jiang, I.H.-R.; Yu, B.; Pan, D.Z.; HUI-RU JIANG | Proceedings of International Conference on ASIC | | | |
2010 | Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles | Jiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | | | |
2016 | OWARU: Free space-aware timing-driven incremental placement | Jung, J.; Nam, G.-J.; Reddy, L.; Jiang, I.H.-R.; Shin, Y.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2009 | POSA: Power-state-aware buffered tree construction | Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2008 | Power-state-aware buffered tree construction | Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG | 26th IEEE International Conference on Computer Design 2008, ICCD | | | |
2013 | PushPull: Short path padding for timing error resilient circuits | Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | | | |
2014 | PushPull: Short-path padding for timing error resilient circuits | Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
2018 | Recent research and challenges in multiple patterning layout decomposition | Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI | | | |
2016 | Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits | Schlichtmann, U.; Hashimoto, M.; Jiang, I.H.-R.; Li, B.; HUI-RU JIANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | | | |
2016 | Resource-aware functional ECO patch generation | Cheng, A.-C.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG | Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 | | | |
2011 | Simultaneous functional and timing ECO | Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 17 | | |
2010 | Simultaneous voltage island generation and floorplanning | Li, H.-Y.; Jiang, I.H.-R.; Chen, H.-M.; HUI-RU JIANG | Proceedings - IEEE International SOC Conference, SOCC 2010 | | | |
2015 | Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations | Jiang, I.H.-R.; Nam, G.-J.; Chang, H.-Y.; Nassif, S.R.; Hayes, J.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2012 | Timing ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
2011 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
2012 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 | |
2008 | Unification of obstacle-avoiding rectilinear steiner tree construction | Jiang, I.H.-R.; Lin, S.-W.; Yu, Y.-T.; HUI-RU JIANG | 2008 IEEE International SOC Conference, SOCC | | | |