公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2015 | Fast lithographic mask optimization considering process variation | Su, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 9 | 0 | |
2016 | Fast lithographic mask optimization considering process variation | Su, Y.-H.; Huang, Y.-C.; Tsai, L.-C.; Chang, Y.-W.; Banerjee, S.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 34 | 30 | |
2012 | Fast timing-model independent buffered clock-tree synthesis | Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 10 | |
2010 | Fast timing-model independent buffered clock-tree synthesis | Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 23 | 0 | |
2018 | First beam tests of prototype silicon modules for the CMS High Granularity Endcap Calorimeter | Akchurin, N.; Apreysan, A.; Banerjee, S.; Barney, D.; Bilki, B.; Bornheim, A.; Bueghly, J.; Callier, S.; Candelise, V.; Chang, Y.-H.; Chang, Y.-W.; Chatterjee, R.; Cheng, K.-Y.; Chien, C.-H.; Rivera, E.C.; Taille, C.D.L.; Eckdahl, J.; Frahm, E.; Frank, N.; Freeman, J.; Gawerc, D.; Gecse, Z.; Ginghu, C.; Gonzalez, H.; Hawke, T.; Incandela, J.; Jain, S.; Jain, S.; Jheng, H.-R.; Jonas, M.; Kara, O.; Khurana, R.; Kopp, G.; Kumar, A.; Kunori, S.; Kuo, C.-M.; Kyre, S.; Lazic, D.; Li, B.; Liao, H.; Lipton, R.; Linssen, L.; Lobanov, A.; Lu, R.-S.; Maier, A.; Majumder, G.; Mannelli, M.; Martelli, A.; Mastrolorenzo, L.; Mengke, T.; Miller, M.; Moll, M.; Morant, J.; Mudholkar, T.; Odell, N.; Paganis, E.; Paulini, M.; Pena, C.; Petiot, P.; Pezzotti, L.; Pitters, F.; Pozdnyakov, A.; Prosper, H.; Psallidas, A.; Quast, T.; Quinn, R.; Romeo, F.; Roy, A.; Rubinov, P.; Rusack, R.; Sicking, E.; Steen, A.; Sun, M.; Tarasov, I.; Thienpont, D.; Tiras, E.; Virdee, T.; Wang, F.; Weinberg, M.; White, D.; Xie, S.; Yu, S.-S.; Zhang, H.; RONG-SHYANG LU ; Stathes Paganis | Journal of Instrumentation | 15 | 11 | |
2006 | Floorplan and power/ground network co-synthesis for fast design convergence | Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 22 | | |
2009 | Floorplanning | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 5 | 0 | |
2007 | FULL-CHIP NANOMETER ROUTING TECHNIQUES | Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J. | | | | |
2008 | Full-chip routing considering double-via insertion | Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B. | IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD) | | | |
2008 | Full-chip routing considering double-via insertion | Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 61 | 46 | |
2012 | Full-field chromatic confocal surface profilometry employing digital micromirror device correspondence for minimizing lateral cross talks | Chen, L.-C.; Chang, Y.-W.; Li, H.-W.; LIANG-CHIA CHEN | Optical Engineering | | | |
2011 | Full-field chromatic confocal surface profilometry employing DMD correspondence for minimizing lateral cross talks | Chen, L.-C.; Li, H.-W.; Chang, Y.-W.; LIANG-CHIA CHEN | Proceedings of SPIE - The International Society for Optical Engineering | | | |
2001 | Generic ILP-based approaches for dynamically reconfigurable FPGA partitioning | Wu, G.-M.; Lin, J.-M.; Chao, M.C.-T.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 0 | 0 | |
2001 | Generic ILP-based approaches for time-multiplexed FPGA partitioning | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 | 22 | |
2000 | Generic universal switch blocks | Shyu, M.; Wu, G.-M.; Chang, Y.-D.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computers | 32 | 28 | |
2009 | Global and Detailed Routing | Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 24 | 0 | |
2003 | Graph matching-based algorithms for array-based FPGA segmentation design and routing | Lin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
2019 | Graph-and ILP-based cut redistribution for two-dimensional directed self-assembly | Wang, Z.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 1 | 0 | |
2012 | Graph-based subfield scheduling for electron-beam photomask fabrication | Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 3 | 0 | |
2013 | Graph-based subfield scheduling for electron-beam photomask fabrication | Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 7 | |