Skip navigation
中文
English
DSpace
CRIS
首頁
單位
研究人員
研究成果檢索
分類瀏覽
單位
研究人員
研究成果檢索
學術出版
幫助
登入
中文
English
NTU Scholars
研究成果檢索
瀏覽 的方式: 作者
J. B. Kuo
或是輸入前幾個字:
跳到:
0-9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
排序方式:
升冪
降冪
結果/頁面
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
作者/紀錄:
全部
1
5
10
15
20
25
30
35
40
45
50
顯示 31 到 50 筆資料,總共 103 筆
< 上一頁
下一頁 >
公開日期
標題
作者
來源出版物
scopus
WOS
全文
2011
Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique
S. F. Huang; R. S. Shen; J. B. Kuo; JAMES-B KUO
Power and Timing Modeling Optimization Symposium
2
0
2005
CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects
Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO
HKEDSSC
0
0
2010
Charge Pumping Behavior of STI-Isolated PD SOI NMOS Device Operating at Low Temp
C. F. Yen; J. B. Kuo; JAMES-B KUO
IEDMS
2002
Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion
S. C. Lin; J. B. Kuo; JAMES-B KUO
IEEE Transactions on Electron Devices
3
1
2009
Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide
C. H. Lin; J. B. Kuo; JAMES-B KUO
Solid State Electronics
1
1
1998
CMOS VLSI Engineering: Silicon-on-Insulator (SOI)
J. B. Kuo; K. W. Su; JAMES-B KUO
2002
Compact Breakdown Model for PD SOI NMOS Devices Considering BJT/MOS Impact Ionization for SPICE Circuits Simulation
J. B. Kuo; S. C. Lin; JAMES-B KUO
IEDMS
2006
Compact Gate Tunneling Current Model Considering Distributed Effect for Sub-100nm NMOS Devices with Ultra-thin (1nm) Gate Oxide
C. H. Lin; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO
IEDMS
2002
Compact LDD/FD SOI CMOS Device Model Considering Energy Transport and Self Heating for SPICE Circuit Simulation
J. B. Kuo; S. C. Lin; JAMES-B KUO
IEDMS
1999
Compact MOS/Bipolar Charge-Control Model of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation---SOI-Technology (ST)-SPICE
J. B. Kuo; K. W. Su; S. C. Lin; JAMES-B KUO
European Solid State Device Research Conference (ESSDERC)
2002
Compact threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices
J. B. Kuo; K. H. Yuan; S. C. Lin; JAMES-B KUO
IEEE Transactions on Electron Devices
7
6
2014
Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs
G. Lin; J. B. Kuo; JAMES-B KUO
ISCAS
6
0
2012
Design of Distortionless Interconnects via Main/auxiliary Structure with LC Line for High Speed On-chip Transmission
T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO
ICSICT
2009
Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique
C. H. Lin; J. B. Kuo; JAMES-B KUO
Power and Timing Optimization Symposium
2012
Floating-Body Kink Effect: Ply-Si TFT versus SOI CMOS
T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO
Eurosoi Conference
2005
Floating-Body Kink-Effect RElated Capacitance Behavior of Nanometer PD SOI NMOS Devices
G. S. Lin; J. B. Kuo; JAMES-B KUO
EDMS
2015
Floating-body-correlated subthreshold behavior of SOI NMOS device considering back-gate-bias effect
S. K. Hu; J. B. Kuo; Y. J. Chen; JAMES-B KUO
Spanish Conference on Electron Devices
0
0
2009
Floating-body-effect-related gate tunneling leakage current phenomenon of 40nm PD SOI NMOS device
H. J. Hung; J. I. Lu; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
EUROSOI
0
0
2009
Floating-Body-Effect-Related Gate Tunneling Leakage Current Phenomenon of 40nm PD SOI NMOS Device
H. J. Hung; J. B. Kuo; C. T. Tsai; D. Chen; JAMES-B KUO
International Semiconductor Devices Research Symposium
0
2012
Foating-Body Kink-Effect Related Parasitic Bipolar Transistor Behavior in Poly-Si TFT
T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO
IEEE Transactions on Electron Devices
8
6