公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1997 | BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. | Jiang, Jie-Hong R.; Jou, Jing-Yang; Huang, Juinn-Dar; Wei, Jung-Shian; JIE-HONG JIANG | Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997 | 0 | 0 | |
1998 | Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. | Jiang, Jie-Hong Roland; Jou, Jing-Yang; Huang, Juinn-Dar; JIE-HONG JIANG | Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998. | 0 | 0 | |
1996 | Easily testable data path allocation using input/output registers | Huang, Li-Ren; Jou, Jing-Yang; Kuo, Sy-Yen ; Liao, Wen-Bin | Test Symposium, 1996. | 0 | 0 | |
1996 | An efficient PRPG strategy by utilizing essential faults | Huang, Li-Ren; Jou, Jing-Yang; Kuo, Sy-Yen | Test Symposium, 1996. | 0 | 0 | |
1999 | Hierarchical Floorplan Design on the Internet. | Lin, Jiann-Horng; Jou, Jing-Yang; Jiang, Iris Hui-Ru; HUI-RU JIANG | Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999 | 0 | 0 | |
2003 | Inductance Modeling for On-Chip Interconnects | Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen ; Chen, Tai-Chen; Jou, Jing-Yang | Analog Integrated Circuits and Signal Processing | 5 | 4 | |
2004 | Layout techniques for on-chip interconnect inductance reduction. | Tu, Shang-Wei; Jou, Jing-Yang; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
1999 | Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. | Jiang, Iris Hui-Ru; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999. | 9 | 0 | |
2000 | Optimal reliable crosstalk-driven interconnect optimization | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG | International Symposium on Physical Design | 7 | | |
2004 | Simultaneous Floorplan and Buffer-Block Optimization | HUI-RU JIANG ; YAO-WEN CHANG ; Jou, Jing-Yang; Chao, Kai-Yuan | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 10 | 2 | |
2003 | Simultaneous floorplanning and buffer block planning. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |