公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2018 | Comprehensive thermal SPICE modeling of FinFETs and BEOL with layout flexibility considering frequency dependent thermal time constant, 3D heat flows, boundary/alloy scattering, and interfacial thermal resistance with circuit level reliability evaluation | Yan J.-Y; Chung C.-C; Jan S.-R; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU | Digest of Technical Papers - Symposium on VLSI Technology | 5 | 0 | |
2020 | Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry | Chung C.-C; Lin H.-C; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU | Digest of Technical Papers - Symposium on VLSI Technology | 3 | 0 | |
2019 | Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs | Chung C.-C; Ye H.-Y; Lin H.H; Wan W.K; Yang M.-T; Liu C.W.; CHEE-WEE LIU | IEEE Electron Device Letters | 11 | 11 |