公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2006 | A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 | 22 | 0 | |
2018 | A 232-to-1996KS/s robust compressive-sensing reconstruction engine for real-time physiological signals monitoring | Chen, T.-S.; Kuo, H.-C. ; Wu, A.-Y. | IEEE International Solid-State Circuits Conference | 9 | 0 | |
2007 | A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2007 IEEE Asian Solid-State Circuits Conference | 3 | 0 | |
2011 | A 0.16nJ/bit/iteration 3.38mm 2 turbo decoder chip for WiMAX/LTE standards | Lin, C.-H.; Chen, C.-Y.; Chang, E.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2011 International Symposium on Integrated Circuits | 9 | 0 | |
2007 | A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system | Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Symposium on VLSI Circuits | 17 | 0 | |
2010 | A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system | Chen, Y.-L.; Jheng, T.-J.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | ESSCIRC 2010 - 36th European Solid State Circuits Conference | 0 | 0 | |
2005 | A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications | Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 5 | 0 | |
2009 | A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications | Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | 0 | |
2008 | A 7.39mm2 76mw (1944, 972) LDPC decoder chip for IEEE 802.11n applications | Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 | 12 | 0 | |
2009 | A channel-adaptive early termination strategy for LDPC decoders | Chen, Y.-H.; Chen, Y.-J.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 9 | 0 | |
2007 | A clock-fault tolerant architecture and circuit for reliable nanoelectronics system | Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU | 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 | 6 | 0 | |
2004 | A design flow for multiplierless linear-phase fir filters: From system specification to verilog code | Jheng, K.-Y.; Jou, S.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2005 | A DVB-T baseband demodulator design based on multimode silicon IPs | Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test | 3 | 0 | |
2004 | A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design | Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | | | |
2005 | A high-speed scalable shift-register based on-chip serial communication design for SoC applications | Wey, I.-C.; Chen, Y.-G.; Wu, C.-T.; Wang, W.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2005 PhD Research in Microelectronics and Electronics | 0 | 0 | |
2006 | A low cost packet detector in OFDM-based ultra-wideband systems | Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | 2 | 0 | |
2012 | A low-complexity grouping FFT-based codebook searching algorithm in LTE system | Lin, Y.-H.; Zhan, C.-Z.; Chu, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 1 | 0 | |
2005 | A memory-reduced Log-MAP kernel for turbo decoder | Tsai, T.-H.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | 9 | 0 | |
2007 | A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network | Shen, W.-T.; Chao, C.-H.; Lien, Y.-K.; Wu, A.-Y.; AN-YEU(ANDY) WU | NOCS 2007: First International Symposium on Networks-on-Chip | 78 | 0 | |
2006 | A new early termination scheme of iterative turbo decoding using decoding threshold | Li, F.-M.; Lin, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | 2 | 0 | |