Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
1993 | Accurate Current Model for CMOS Gates | Wang, J. H.; Fan, J. T.; 馮武雄; Feng, Wu-Shiung | JTC-CSCC'93:1993 Joint Technical Conference on Circuit/Systems, Computers and Communications | | | |
1994 | An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits | Wang, J. H.; Chang, M. L.; 馮武雄; Feng, Wu-Shiung | EDAC: the European Design Automation Conference | | | |
1990 | An Alternating Router for Compacted Routing Area | Tsai, C. C.; 陳少傑 ; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | 1990 2nd Workshop on CAD for VLSI | | | |
1991 | An Analog Neural Network Approach to Global Routing Problem | Shih, P. H.; 馮武雄; Feng, Wu-Shiung | An International Journal on Cybernetics and System | | | |
1992 | An Analytical CMOS Inverter Delay Model Including Channel-Length Modulations | Chow, H. C.; 馮武雄; Feng, Wu-Shiung | IEEE Journal of Solid-State Circuits | | | |
1990 | An Application of an Expert System in Layout Compaction of VlSI Design | Hsiao, P. Y.; 馮武雄; Chen, H. F.; Feng, Wu-Shiung | Journal of the Chinese Institute of Engineers | | | |
1991 | An Application of Neural Network on Channel Routing Problem | Shih, P. H.; 馮武雄; Feng, Wu-Shiung | Parallel Computing | | | |
1987 | Automatic Floorplan and Placement for Hierarchical Layout System | Chen, J. Y.; 馮武雄; Feng, Wu-Shiung | 1987 Electron Devices and Materials Symposium, Taipei(1987.09) | | | |
1985 | Automatic VLSI Circuit Synthesizer System Vol.1:A Programming Logic Array (PLA) Reduction and Generation System | 馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1985 | Automatic VLSI Circuit Synthesizer System Vol.2:Data Path Synthesizer | 馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1985 | Automatic VLSI Circuit Synthesizer System Vol.3:Design and Imple Mentation of a Hardware Compiler Optimizer | 馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Yu, Hui-Jung | | | | |
1993 | BTS-Binary-Tree Timing Simulator with the Considerations of Internal Charges | Wang, J. H.; Fan, J. T.; 馮武雄; Feng, Wu-Shiung | IEEE Proceedings. E, Computer and digital techniques | | | |
1992 | Channel Routing Using Neural Networking | Shih, P. H.; 馮武雄; Feng, Wu-Shiung | Journal of the Chinese Institute of Engineers | | | |
1994 | Charge-Based Current Model for CMOS Gates | Wang, J. H.; Fan, J. T.; 馮武雄; Feng, Wu-Shiung | Electronics Letters. 22nd | | | |
1993 | Computer-Aided Design on the VLSI 45-Degree Mask Compaction | 馮武雄; 楊維楨; Hsieh, M. Y.; Feng, Wu-Shiung; Yang, Wei-Tzen | TENCON'93, Beijing(1993.10.19-10.21) | | | |
1992 | Considerations of Internal Charges on Computing Delay | Wang, J. H.; Chang, M.; 馮武雄; Feng, Wu-Shiung | The 3rd | | | |
1989 | Constrained Via Minimization for Three-Layer Routing | Chang, K. E.; Jyu, H. F.; 馮武雄; Feng, Wu-Shiung | Computer-Aided Design | | | |
1991 | Constrained Via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems | Fang, S. C.; Chang, K. E.; 馮武雄; 陳少傑 ; Feng, Wu-Shiung; Chen, Sao-Jie | Design Automation Conference | | | |
1989 | The Control Model for a Knowledge-Based Approach to VLSI Compaction Design | Chen, S. F. Steven; Hsiao, P. Y.; 馮武雄; Wang, W. T.; Dai, S. N.; Feng, Wu-Shiung | International Federation for Information Processing, the 11th World Computer Congress, San Francisco, CA(1989.08) | | | |
1995 | A Current Waveform Simulator Using Charge-Bsed Current Model | 馮武雄; Wang, J. H.; Fan, J. T.; Feng, Wu-Shiung | Journal of the Chinese Institute of Engineers | | | |