公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2008 | Effective Wire Models for X-Architecture Placement | Chen, Tung-Chieh; Chuang, Yi-Lin; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | 1 | |
2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. | Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
2006 | Modern Floorplanning Based on B?-Tree and
Fast Simulated Annealing | Chen, Tung-Chieh; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
2005 | Modern floorplanning based on fast simulated annealing. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 | 59 | 0 | |
2007 | MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. | Chen, Tung-Chieh; Yuh, Ping-Hung; Chang, Yao-Wen; Huang, Fwu-Juh; Liu, Denny; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
2008 | A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning | Chen, Tung-Chieh; Chang, Yao-Wen ; Lin, Shyh-Chang | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | 24 | |
2006 | NTUplace2: a hybrid placer using partitioning and analytical techniques. | Jiang, Zhe-Wei; Chen, Tung-Chieh; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 0 | 0 | |
2007 | NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs. | Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Modern Circuit Placement, Best Practices and Results | | | |
2005 | NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. | Chen, Tung-Chieh; Hsu, Tien-Chang; Jiang, Zhe-Wei; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 | 0 | 0 | |
2008 | Packing Floorplan Representations. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Handbook of Algorithms for Physical Design Automation. | | | |
2005 | SoC test scheduling using the B*-tree based floorplanning technique | Wuu, Jen-Yi; Chen, Tung-Chieh; Chang, Yao-Wen | Asia and South Pacific Design Automation Conference, ASP-DAC 2005 | 0 | 0 | |