公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2009 | Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits | Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu ; Chen, Jie | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2004 | A fast and power-saving self-timed Manchester carry-bypass adder for Booth multiplier-accumulator design | Wey, I-Chyn; Chow, Hwang-Cherng; Chen, You-Gang; Wen, An-Yeu | Advanced System Integrated Circuits 2004 | 0 | 0 | |
2007 | Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. | AN-YEU(ANDY) WU ; Ye, Jhao-Ji; Chen, You-Gang; Wey, I-Chyn; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | | | |