公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2018 | Analysis of heterojunction GaAs1-xSbx/In1-yGayAs tunnel FETs considering line tunneling | Wang C.-T; Hu V.P.-H.; VITA PI-HO HU | Proceedings - 2018 7th International Symposium on Next-Generation Electronics, ISNE 2018 | 0 | 0 | |
2018 | Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation | Chiu P.-C; Hu V.P.-H.; VITA PI-HO HU | 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings | 4 | 0 | |
2017 | Analysis of subthreshold swing and internal voltage amplification for hysteresis-free negative capacitance FinFETs | Chiu P.-C; Hu V.P.-H.; VITA PI-HO HU | 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings | 5 | 0 | |
2019 | Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power Applications | Gupta M; Hu V.P.-H.; VITA PI-HO HU | 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 | 0 | 0 | |
2019 | Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET | Lin H.-H; Hu V.P.-H.; VITA PI-HO HU | Proceedings - International Symposium on Quality Electronic Design, ISQED | 4 | 0 | |
2018 | Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling | Wang C.-T; Hu V.P.-H.; VITA PI-HO HU | 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings | 4 | 0 | |
2019 | Evaluation of analog circuit performance for ferroelectric SOI MOSFETs considering interface trap charges and gate length variations | Lu Y.-C; Hu V.P.-H.; VITA PI-HO HU | 2019 Silicon Nanoelectronics Workshop, SNW 2019 | 7 | 0 | |
2019 | Improved read stability and writability of negative capacitance FinFET SRAM cell for subthreshold operation | Zheng Z.-A; Hu V.P.-H.; VITA PI-HO HU | Proceedings - IEEE International Symposium on Circuits and Systems | 7 | 0 | |
2021 | Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors | Gupta M; Hu V.P.-H.; VITA PI-HO HU | ECS Journal of Solid State Science and Technology | 2 | 2 | |
2019 | Reduced RTN amplitude and single trap induced variation for ferroelectric FinFET by substrate doping optimization | Lin Z.-T; Hu V.P.-H.; VITA PI-HO HU | 2019 Silicon Nanoelectronics Workshop, SNW 2019 | 1 | 0 | |
2020 | Subthreshold Behavior of Ferroelectric Junctionless Transistor | Hu V.P.-H.; VITA PI-HO HU | 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 | 0 | 0 | |