公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2007 | Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis | CHIEN-MO LI ; J. C.-M. Li; Hung-Mao Lin; Fang Min Wang; CHIEN-MO LI | IEEE Transactions on Computers | |||
2010 | DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in | CHIEN-MO LI ; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1 | ||
2005 | Effective and Economic Phase Noise Testing for Single Chip TV Tuners | CHIEN-MO LI ; P.C. Lin; J. C.-M. Li; Chih-Ming Chiang; Chuo-Jan Pan; CHIEN-MO LI | VLSI/CAD Symposium | |||
2008 | Effective and Economic Phase Noise Testing for Single-Chip TV Tuners | CHIEN-MO LI ; J. C.-M. Li; P.-C. Lin; P.-C. Chiang; C.-M. Pan; C.W. Tseng; CHIEN-MO LI | IEEE Transactions on Instrumentation and Measurement | 0 | ||
2009 | Electronic Design Automation | CHIEN-MO LI ; J. C.-M. Li; M. Hsiao; CHIEN-MO LI | ||||
2014 | GPU-Based Timing-Aware Test Generation for Small Delay Defects | CHIEN-MO LI ; K.Y. Liao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI | IEEE European Test Symposium | |||
2008 | Phase Noise Testing of Single Chip TV Tuners, | CHIEN-MO LI ; P.-C. Lin; C.-H. Hsu; J. C.-M. Li; C.-M. Chiang; C.-J. Pan,; CHIEN-MO LI | IEEE VLSI-DAT | |||
2011 | Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan | CHIEN-MO LI ; R.Y. Wen; Y.C. Huang; M.H. Tsai; K.Y. Liao; J. C.-M. Li; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; H.-C. Li; CHIEN-MO LI | International Test Conference |