公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2010 | 3D-PIC: An Error Tolerant 3D CMOS Imager | H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG | 3D Integration Workshop | |||
2013 | A circular pipeline processing based deterministic parallel test pattern generator | K.-W. Yeh; J.-L. Huang; H.-J. Chao; L.-T. Wang; JIUN-LANG HUANG | International Test Conference | 9 | 0 | |
2009 | A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input | X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG | International Journal of Electrical Engineering | |||
2012 | A fault-tolerant PE array based matrix multiplier design | B.-Y. Jan; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 0 | 0 | |
2009 | A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method | K.-W. Yeh; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | International Conference on Algorithms and Architectures for Parallel Processing | 10 | 0 | |
2007 | A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing | T.-L. Hung; J.-L. Huang; JIUN-LANG HUANG | VLSI Test Symposium | 2 | 0 | |
2013 | A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers | H.-M. Chang; J.-L. Huang; D.-M. Kwai; K.-T. Cheng; C.-W. Wu; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 6 | 6 | |
2013 | A mutual characterization based SAR ADC self-testing technique | H.-J. Lin; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
2011 | A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager | X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
2006 | A routability constrained scan chain ordering technique for test power reduction | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 8 | ||
2012 | A SAR ADC missing-decision level detection and removal technique | X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | VLSI Test Symposium | 0 | 0 | |
2010 | A scalable quantitative measure of IR-drop for scan pattern generation | M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG | International Conference on Computer-Aided Design | 4 | 0 | |
2008 | A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization | P.-H. Chiu; J.-L. Huang; JIUN-LANG HUANG | International Symposium on Flexible Electronics and Displays | |||
2011 | A self-testing and calibration method for embedded successive approximation register ADC | X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 11 | 0 | |
2008 | A Self-Testing and Calibration Technique for Current-Steering DACs | Y.-L. Ma; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 4 | 0 | |
2009 | A Self-Testing Assisted Pipelined-ADC Calibration Technique | J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG | International Conference on ASIC | |||
2015 | A Test-Application-Count Based Learning Technique for Test Time Reduction | G.-Y. Lin; K.-H. Tsai; J.-L. Huang; W.-T. Cheng; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 3 | 0 | |
2012 | A transition isolation scan cell design for low shift and capture power | Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG | Asian Test Symposium | 13 | 0 | |
2011 | ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 16 | 14 | |
2007 | An Efficient Peak Power Reduction Technique for Scan Testing | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 18 | 0 |