| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
|---|---|---|---|---|---|---|
| 2014 | A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects | Wen-En Wei; Hung-Yi Li; Cheng-Yu Han; James Chien-Mo Li; Jian-Jang Huang; I-Chun Cheng; Chien-Nan Liu; Yung-Hui Yeh; I-CHUN CHENG ; JIAN-JANG HUANG ; CHIEN-MO LI | Journal of Display Technology | 5 | 2 | |
| 2008 | Diagnosis of Logic-chain Bridging Faults | Wei-Chih Liu; Wei-Lin Tsai; Hsiu-Ting Lin; James Chien-Mo Li; CHIEN-MO LI | IEEE Int’l Workshop on RTL and High Level Testing | 0 | 0 | |
| 2019 | DR-scan: Dual-rail Asynchronous Scan DfT and ATPG | Shih-An Hsieh; Ying-Hsu Wang; Ting-Yu Shen; Kuan-Yen Huang; Chia-Cheng Pai Tsai-Chieh Chen; James Chien-Mo Li; CHIEN-MO LI | IEEE Transactions on Computer Aided Design | 2 | 2 | |
| 2008 | IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores | Geng-Ming Chiu; C.-Y. Chiu; R-Y. Wen; James Chien-Mo Li; CHIEN-MO LI | International Test Conference | 4 | 0 | |
| 2015 | TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for Cell-internal Defects | A.F. Lin; Kuan-Yu Liao; Kuan-Ying Chiang; James Chien-Mo Li; CHIEN-MO LI | IEEE VLSI/DAT | 4 | 0 | |
| 2013 | Test Generation of Path Delay Faults Induced by Defects in Power TSV | Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI | IEEE Asian Test Symposium | 2 | 0 | |
| 2013 | Testing Leakage Faults of Power TSV in 3D IC | Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI | IEEE Int’l workshop on 3D IC | |||
| 2009 | Transition Fault Diagnosis Using At-speed Test Patterns | Shang-Feng Chao; Jheng-Yang Ciou; James Chien-Mo Li; CHIEN-MO LI | IEEE Int’l Workshop on RTL and High Level Testing |
