Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
2007 | A statistical approach to the timing-yield optimization of pipeline circuits | Hsu, C.-H.; Chou, S.-J.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG | Lecture Notes in Computer Science | 0 | | |
2011 | Ashenhurst decomposition using SAT and interpolation | Lin, H.-P.; Jiang, J.-H.R.; Lee, R.-R.; JIE-HONG JIANG | Advanced Techniques in Logic Synthesis, Optimizations and Applications | 0 | 0 | |
2011 | Bi-decomposition using SAT and interpolation | Lee, R.-R.; Jiang, J.-H.R.; Hung, W.-L.; JIE-HONG JIANG | Advanced Techniques in Logic Synthesis, Optimizations and Applications | 0 | 1 | |
2019 | Biochemical Threshold Function Implementation with Zero-Order Ultrasensitivity | Huang, W.-C.; Jiang, J.-H.R.; Fages, F.; Molina, F.; JIE-HONG JIANG | BioCAS 2019 - Biomedical Circuits and Systems Conference, Proceedings | 1 | 0 | |
2019 | Comprehensive search for ECO rectification using symbolic sampling | Kravets, V.N.; Lee, N.-Z.; Jiang, J.-H.R.; JIE-HONG JIANG | Proceedings - Design Automation Conference | 6 | 0 | |
2011 | Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization | Chang, C.-W.; Chou, H.-Z.; Chang, K.-H.; Jiang, J.-H.R.; Liu, C.-N.J.; Hsiao, C.-H.; JIE-HONG JIANG ; SY-YEN KUO | Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 | 3 | 0 | |
2019 | Disjoint-support decomposition and extraction for interconnect-driven threshold logic synthesis | Chen, H.; Hung, S.-C.; Jiang, J.-H.R.; JIE-HONG JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
2018 | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction | Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI | Design Automation Conference | 5 | 0 | |
2020 | Engineering Change Order for Combinational and Sequential Design Rectification | Jiang, J.-H.R.; Kravets, V.N.; Lee, N.-Z.; JIE-HONG JIANG | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 | 8 | 0 | |
2011 | Extracting functions from boolean relations using SAT and interpolation | Jiang, J.-H.R.; Lin, H.-P.; Hung, W.-L.; JIE-HONG JIANG | Advanced Techniques in Logic Synthesis, Optimizations and Applications | 0 | 0 | |
2004 | Functional dependency for verification reduction | Jiang, J.-H.R.; Brayton, R.K.; JIE-HONG JIANG | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | 18 | | |
2020 | Learning to Automate the Design Updates from Observed Engineering Changes in the Chip Development Cycle | Kravets, V.N.; Jiang, J.-H.R.; Riener, H.; JIE-HONG JIANG | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 | 3 | 0 | |
2018 | Recombinase-based genetic circuit optimization | Lai, C.-N.; Jiang, J.-H.R.; Fages, F.; JIE-HONG JIANG | 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings | 1 | 0 | |
2003 | Reducing multi-valued algebraic operations to binary | Jiang, J.-H.R.; Mischenko, A.; Brayton, R.K.; JIE-HONG JIANG | Proceedings -Design, Automation and Test in Europe, DATE | 3 | 0 | |
2012 | Reducing test point overhead with don't-cares | Chang, K.-H.; Chang, C.-W.; Jiang, J.-H.R.; Liu, C.-N.J.; JIE-HONG JIANG | Midwest Symposium on Circuits and Systems | 2 | 0 | |
2019 | Searching parallel separating hyperplanes for effective compression of threshold logic networks | Lee, S.-Y.; Lee, N.-Z.; Jiang, J.-H.R.; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 5 | 0 | |
2016 | Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummification | Chiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | 4 | |
2019 | Time-frame folding: Back to the sequentiality | Chien, P.-C.; Jiang, J.-H.R.; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 2 | 0 | |
2012 | TRECO: Dynamic technology remapping for timing engineering change orders | Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 8 | |