公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2001 | Converter-free multiple-voltage scaling techniques for low-power CMOS digital design | Yeh, Y.-J.; Kuo, S.-Y.; Jou, J.-Y.; SY-YEN KUO | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 23 | 0 | |
2014 | Efficient coverage-driven stimulus generation using simultaneous SAT solving, with application to SystemVerilog | Cheng, A.-C.; Yen, C.-C.; Val, C.G.; Bayless, S.; Hu, A.J.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG | ACM Transactions on Design Automation of Electronic Systems | 3 | 3 | |
1997 | Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR | Huang, L.-R.; Jou, J.-Y.; Kuo, S.-Y.; SY-YEN KUO | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 33 | 17 | |
2004 | Layout techniques for on-chip interconnect inductance reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | | |
2016 | Resource-aware functional ECO patch generation | Cheng, A.-C.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG | Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 | 11 | | |
2006 | RLC coupling-aware simulation and on-chip bus encoding for delay reduction | Tu, S.-W.; Jou, J.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 37 | 23 | |
2005 | Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 6 | 0 | |
2004 | RLC effects on worst-case switching pattern for on-chip buses | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 10 | | |
2003 | Simultaneous floorplanning and buffer block planning | Hui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 11 | 0 | |
1998 | Static power analysis for power-driven synthesis | Yuan, S.-Y.; Chen, K.-H.; Jou, J.-Y.; Kuo, S.-Y. | Computers and Digital Techniques, IEE Proceedings- | | | |
1998 | Static power analysis for power-driven synthesis | Yuan, S.-Y.; Chen, K.-H.; Jou, J.-Y.; Kuo, S.-Y.; SY-YEN KUO | IEE Proceedings: Computers and Digital Techniques | 0 | 0 | |
2001 | Unified functional decomposition via encoding for FPGA technology mapping | Jiang, J.-H.; Jou, J.-Y.; Huang, J.-D.; JIE-HONG JIANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 4 | 3 | |