公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2003 | A fast locking and low jitter delay-locked loop using DHDL | Hsiang-Hui Chang; Jyh-Woei Lin; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 18 | 12 | |
2001 | A fast-lock mixed-mode DLL Using a 2-b SAR Algorithm | Giang-Kaai Dehng; Jyh-Woei Lin; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 38 | 32 | |
2002 | A wide-range delay-locked loop with a fixed latency of one clock cycle | Hsiang-Hui Chang; Jyh-Woei Lin; Ching-Yuan Yang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 147 | 112 |