公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2013 | A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers | H.-M. Chang; J.-L. Huang; D.-M. Kwai; K.-T. Cheng; C.-W. Wu; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 6 | 6 | |
1998 | A New Extended Finite State Machine (EFSM) Model for RTL Design Verification | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
2007 | Chap. 11 Software-Based Self-Testing | J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | System on Chip Test Architectures | |||
2015 | Design, automation, and test for low-power and reliable flexible electronics | T.-C. Huang; JIUN-LANG HUANG ; K.-T. Cheng | Foundations and Trends in Electronic Design Automation | 10 | 0 | |
1998 | Libra - A Library-Independent Framework for Post-Layout Performance Optimization | R.C.-Y. Huang; Y. Wang; K.-T. Cheng; CHUNG-YANG HUANG | International Symposium on Physical Design | |||
2011 | Robust Circuit Design for Flexible Electronics | T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | IEEE Design & Test of Computers | 13 | 10 | |
1999 | Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
2001 | Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |