公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2001 | A bipartition-codec architecture to reduce power in pipelined circuits | Shanq-Jang Ruan; Rung-Ji Shang; Feipei Lai; Kun-Lin Tsai; FEI-PEI LAI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | ||
2005 | A Low Power Scheduling Method Using Dual Vdd and Dual Vth | Kun-Lin Tsai; Szu-Wei Chang; Feipei Lai; Shanq-Jang Ruan; FEI-PEI LAI | IEEE International Symposium on Circuits and Systems | |||
2011 | A Priority Based Output Arbiter for NoC Router | Cheng-Hao Chan; Kun-Lin Tsai; Feipei Lai; Shun-Hung Tsai; FEI-PEI LAI | The 2011 IEEE International Symposium on Circuits and Systems | |||
2001 | An Entropy-Based Algorithm to Reduce Area Overhead for Bipartition-Codec Architecture | Po-Hung Chen; Shanq-Jang Ruan; Kuen-Pin Wu; Dai-Xun Hu; Feipei Lai; Kun-Lin Tsai; FEI-PEI LAI | 2001 IEEE International Symposium on Circuits and Systems | |||
2004 | Circuit Partition and Reordering Technique for Low Power IP | Kun-lin Tsai; Shanq-jang Ruan; Chun-ming Huang; Edwin Naroska; FEI-PEI LAI | IEICE Transactions on Electronics | |||
2005 | Low Power Dynamic Bus Encoding for Deep Sub-micron Design | Kun-Lin Tsai; Shanq-Jang Ruan; Li-Wei Chen; Feipei Lai; Edwin Naroska; FEI-PEI LAI | International IEEE Northeast Workshop on Circuits & Systems | |||
2006 | Low Power Scheduling Method using Multiple Supply Voltages | Kun-Lin Tsai; Ju-Yueh Lee; Shanq-Jang Ruan; FEI-PEI LAI | EEE International Symposium on Circuits and Systems | |||
2003 | State Reordering for Low Power Combinational Logic | Kun-Lin Tsai; Feipei Lai; Shanq-Jang Ruan; Szu-Wei Chang; FEI-PEI LAI | 8th Asia-Pacific Conference, ACSAC 2003 | |||
2006 | Using MR Thermometry to Monitor the Frozen Effect in High-Temperature Superconducting RF Coil System | Li-Wei Kuo; Ching Yao; Kun-Lin Tsai; Hong-Chang Yang; Jyh-Horng Chen; JYH-HORNG CHEN | 14th ISMRM Ann Meeting |