公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2011 | An at-speed self-testable technique for the high speed domino adder | Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Liu, C.-W.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | Proceedings of the Custom Integrated Circuits Conference | 1 | 0 | |
2012 | An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder example | Wang, Y.-S.; Hsieh, M.-H.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | IEEE Transactions on Circuits and Systems I: Regular Papers | 3 | 3 | |
2019 | ATPG and test compression for probabilistic circuits | Yang, K.-C.; Lee, M.-T.; Wu, C.-H.; Li, J.C.-M.; CHIEN-MO LI | 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 | 2 | 0 | |
2017 | Automatic test pattern generation | Cheng, K.-T.T.; Wang, L.-C.; Li, H.; Li, J.C.-M.; CHIEN-MO LI | Electronic Design Automation for IC System Design, Verification, and Testing | 0 | 0 | |
2010 | CSER: BISER-based concurrent soft-error resilience | Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI ; JIUN-LANG HUANG | VLSI Test Symposium (VTS) | 2 | 0 | |
2018 | Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations | Li, Y.-C.; Lin, S.-Y.; Lin, H.-Y.; Li, J.C.-M.; CHIEN-MO LI | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 | 1 | 0 | |
2009 | Fault Simulation and Test Generation | Li, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI | Electronic Design Automation | 2 | 0 | |
2016 | A multicircuit simulator based on inverse jacobian matrix reuse | Lee, H.-I.; Han, C.-Y.; Li, J.C.-M.; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
2018 | Parallel order ATPG for test compaction | Chen, Y.-W.; Ho, Y.-H.; Chang, C.-M.; Yang, K.-C.; Li, M.-T.; Li, J.C.-M.; CHIEN-MO LI | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 | 5 | 0 | |
2011 | Placement optimization of flexible TFT digital circuits | Liu, W.-H.; Ma, E.-H.; Wei, W.-E.; Li, J.C.-M.; CHIEN-MO LI | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 1 | 0 | |
2016 | Power-supply-noise-aware timing analysis and test pattern regeneration | Han, C.-Y.; Li, Y.-C.; Kan, H.-T.; Li, J.C.-M.; CHIEN-MO LI | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 0 | 0 | |
2010 | Reliability screening of a-Si TFT circuits: Very-low voltage and I <inf>DDQ</inf> Testing | Shen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG ; CHIEN-MO LI | IEEE/OSA Journal of Display Technology | 2 | 1 | |
2017 | Robust test pattern generation for hold-time faults in nanometer technologies | Ho, Y.-H.; Chen, Y.-W.; Chang, C.-M.; Yang, K.-C.; Li, J.C.-M.; CHIEN-MO LI | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 | 1 | 0 | |
2008 | Simultaneous capture and shift power reduction test pattern generator for scan testing | Lin, H.-T.; Li, J.C.-M. | IET Computers & Digital Techniques | | | |
2010 | Static timing analysis for flexible TFT circuits | Chao-Hsuan Hsu; Liu, C.; En-Hua Ma; Li, J.C.-M.; CHIEN-MO LI | Design Automation Conference (DAC) | 5 | 0 | |
2013 | Test generation of path delay faults induced by defects in power TSV | Shih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; TZONG-LIN WU ; YI-CHANG LU ; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 2 | 0 | |
2019 | Test methodology for PCHB/PCFB Asynchronous Circuits | Shen, T.-Y.; Pai, C.-C.; Chen, T.-C.; Li, J.C.-M.; CHIEN-MO LI | Proceedings - International Test Conference | 1 | 0 | |
2018 | Test pattern compression for probabilistic circuits | Chang, C.-M.; Yang, K.-J.; Li, J.C.-M.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 0 | 0 | |
2016 | Test Pattern Modification for Average IR-Drop Reduction | Ding, W.-S.; Hsieh, H.-Y.; Han, C.-Y.; Li, J.C.-M.; Wen, X.; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 9 | 5 | |