公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2002 | A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay | Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan | Custom Integrated Circuits Conference, 2002 | 0 | 0 | |
2001 | A fast-lock mixed-mode DLL using a 2-b SAR algorithm | Dehng, Guang-Kaai; Lin, Jyh-Woei; Liu, Shen-Iuan | IEEE Custom Integrated Circuits Conference | 0 | 32 | |
2002 | A wide-range and fixed latency of one clock cycle delay-locked loop | Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan | IEEE International Symposium on Circuits and Systems | 0 | 0 | |