公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2008 | Power integrity chip-package-PCB co-Simulation for I/O interface of DDR3 high-speed memory | H.-H. Chuang; S.-J. Wu; M.-Z. Hong; D. Hsu; R. Huang; T.-L. Wu; TZONG-LIN WU | Elect. Design Adv. Packag. Systems Symp. | 12 | 0 | |
2009 | Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfaces | H.-H. Chuang; C.-J. Hsu; M.-Z. Hong; D. Hsu; R. Huang; L.-C. Hsiao; T.-L. Wu; TZONG-LIN WU | IEEE Electron. Design Adv. Packag. Systems Symp. | 8 | 0 |